Senior ASIC/RTL Design Engineer

San Jose, CA, US • Posted 8 hours ago • Updated 8 hours ago

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Skills

ARM Architecture
ASIC
AXI
Collaboration
Communication
Computer Hardware
Debugging
Documentation
IP

Summary

We are looking for Senior ASIC/RTL Design Engineer for our client in San Jose, CA

Job Title: Senior ASIC/RTL Design Engineer

Job Location: San Jose, CA

Job Type: Contract

Job Description:

Pay Range: $62.45hr - $78.78hr

The ASIC/RTL Design Engineer Senior is responsible for designing, implementing, and owning major RTL blocks for SoC development.
This role involves close collaboration with architecture, verification, and physical design teams to deliver high-quality designs that meet functional, timing, area, and power requirements and support successful silicon tape-out and bring-up.

Responsibilities:

Write micro-architecture documentation and own major portions of design and implementation.
Design and implement RTL blocks to meet functional, timing, area, and power requirements.
Collaborate with architecture and hardware teams to understand and refine requirements.
Work closely with verification and physical design teams to ensure high-quality design and successful tape-out.
Design and implement logic to support efficient test and debug.
Participate in silicon bring-up for owned features.
Contribute within cross-functional teams to solve complex and novel technical problems.
Implement automation to improve design team efficiency.

Requirement/Must Have:

Five to six plus years of experience in ASIC design.
Proven track record of ASIC design with multiple production tape-outs.
Experience designing RTL blocks for SoC environments.
Experience integrating ASIC IP into SoC designs.
Experience with synthesis, static timing analysis, and timing optimization.

Experience:

Extensive hands-on experience in RTL design and ASIC development for production silicon.

Should Have:

Experience writing timing constraints and exceptions.
Experience with automation and scripting using Perl, Python, or Tcl.
Experience with power-saving and low-power design techniques.
Experience with Arm architecture and protocols such as APB, AXI, and CHI.
Experience with interconnect-based designs.

Skills:

Ability to develop clear and concise engineering documentation.
Ability to organize and present complex technical information.
Strong verbal and written communication skills.

Qualification And Education:

Bachelor s degree required.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10516350
Position Id: CA_SARD_0121
Posted 8 hours ago

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Senior ASIC/RTL Design Engineer

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Job Details

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