RTL-Synthesis CAD Engineer

Company:
Qualcomm Technologies, Inc.

Job Area:
Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Join QCOM Technologies Inc vibrant Global CAD team pushing the limits of RTL and Synthesis solutions for the Snapdragon chips powering billions of mobile devices. The position requires SystemVerilog knowledge, Synthesis or/and Place and Route exposure and CAD development skills to define and develop implementation tools and methodologies for PPA, shortening design cycle time, in close collaboration with Snapdragon Design and Implementation teams. Qualcomm is using leading edge internal and EDA technologies in the Implementation domain, including pioneering in genAI/ML, and developing good-by-construction automation and PPA recipes for the most complex designs of the industry in terms of multi-voltage and Fmax-area-power goals.

This role requires the candidate to be onsite in San Diego, CA.

This role's responsibilities will include:

• Participating to the development of Qualcomm RTL Optimization engine and methods, leveraging both design analytics and GenAI techniques.
• Improving the SoC Synthesis and DFT Stitch methodologies for diverse Mobile, Compute, AI, IoT Snapdragon chips.
• Enabling new features from EDA tools or/and internal tools for RTL PPA, RTL Analysis, Synthesis and DFT Stitch.
• Support Snapdragon design teams on CAD solutions, analyze their requests, and address their requests through ticket queues.
• Interfacing with EDA vendors to enable production-ready tool sets that satisfy project's requirement.
• Setting up, augmenting, and maintaining a regression of complex RTL Opt and Synthesis testcases.
• Innovating with design/tool/flow techniques for area reduction, dynamic power reduction and turn-around time, leading to participation to patents.

Preferred Qualifications:
Bachelor of Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
1-4 years of experience in VLSI CAD, preferably RTL analysis, Synthesis, DFT
1-4 years of experience with scripting tools and programming languages: Python and TCL preferred.

Principal Duties and Responsibilities:
Participate to Synthesis and DFT Stitch flows enablement for foundry advanced process nodes.
Participate to the tuning of design recipes at RTL Opt and Synthesis levels to address specific objectives such as area, turn-around time on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.
Participate along with Qualcomm talented AI team to R&D initiatives driving differentiation in terms of die area reduction, dynamic power, performance and turn-around time.
Participate to the specification of new CAD solutions addressing the PPA requirements of the design teams, in the RTL Opt and Synthesis domains.
Deep dive on Implementation issues, such as cell legalization issues, congestion hotspots, DFT stitch failures etc.
Interface and drive EDA vendor Application Engineers on the resolution of block convergence problems faced by the Snapdragon design teams.

Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field.

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Pay range and Other Compensation & Benefits:
$98,500.00 - $147,700.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.