Design Verification Engineer Engineer with EDA ,RTL Architecture , CAD ,VCS and IES exp - Austin TX - Onsite work

Design Verification Engineer Engineer with EDA ,RTL Architecture , CAD ,VCS and IES exp - Austin TX - Onsite work

Role: Front-End Infrastructure Engineer - 530091

Location: Austin, TX

Duration: 6 Months + extension

Client: Samsung SARC

The FE Infrastructure team is seeking a highly skilled and motivated Engineer with extensive experience in Front-End (FE) flows, tools, and methodologies. This role requires deep technical expertise and experience across multiple verification tools and platforms, as well as a track record of solving complex challenges in FE infrastructure. Candidates should possess a specialized skill set that encompasses regression management, tool deployment, and extensive interaction with industry-leading EDA vendors.

* Development & Maintenance of Verification Flows: You design, support, and continuously improve highly complex, scalable, and efficient Verification flows, with a focus on ensuring robustness and efficiency. Collaborate on advanced flow-based regression tools and maintain them by providing consistent support and updates to meet evolving project demands.

* Regression Management & Triage: You lead regression management systems, including flow-based regression support. Proactively manage regression triage, interactive user requirements, and troubleshoot issues to ensure seamless project continuity. Expertise in debugging and resolving issues related to coverage, regression fail triaging, and flow stability.

* EDA Tool & Vendor Management: You act as the point of contact for VCS Synopsys issues, providing in-depth debugging, troubleshooting, and solutions to complex problems. Regularly liaise with Synopsys vendors and other EDA partners to coordinate tool support, resolve escalated issues, and stay updated on new developments, maintaining an open line of communication to ensure high-quality support for verification processes.

* RTL Architecture Tool Deployment & Support: You will successfully deploy and maintain tools for RTL Architecture, ensuring integration with FE verification flows and addressing any support requirements.

* Version Control Expertise: You leverage extensive knowledge of Git.

Requirements

* 10+ years of experience with a Bachelor s Degree in Computer Science/Engineering, or 8+ years of experience with a master s degree, or 6+ years of experience with a PhD

* Proven experience in designing, maintaining, and troubleshooting FE Design Verification flows and CAD infrastructure for large-scale, high-performance projects.

* Expertise in flow-based regression management, with strong analytical skills in debugging regression and coverage issues.

* Familiarity with industry-standard tools including Synopsys VCS, IES, and RTL architecture tools, with hands-on experience in xprop configuration for VCS and IES.

* Advanced knowledge of version control systems, particularly Git, Perforce, and Git-P4 interfaces, with an ability to support and streamline versioning workflows.

* Strong communication skills, with experience working directly with EDA vendors to resolve issues and improve tool performance.

* Ability to work independently and as part of a team, with a proactive approach to problem-solving and a strong attention to detail.