Design Verification Engineer Jobs in San Jose, CA

1 - 20 of 214 Jobs

Design Verification EngineerJob Title - Design Verification Engineer

SivaltechCompany Name - Sivaltech

•

Santa Clara, California, USA

Contract, Third Party

Job Title: Design Verification Engineer (DV) Company: Sivaltech Location: Santa Clara, CA Job Type: Full-time About Sivaltech: Sivaltech is a leading technology company driving innovation in the industry. We're seeking an experienced Design Verification Engineer to join our team in Santa Clara, CA. Job Description: As a Design Verification Engineer, you'll develop and execute verification plans for complex digital designs, focusing on Ethernet PHY or PCS. You'll work closely with cross-functiona

Design Verification EngineerJob Title - Design Verification Engineer

Mirafra IncCompany Name - Mirafra Inc

•

San Jose, California, USA

Full-time

Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prot

ASIC Design Verification EngineerJob Title - ASIC Design Verification Engineer

TranSquared incCompany Name - TranSquared inc

•

San Jose, California, USA

Contract

Job Title:- ASIC Design Verification Engineer Duration:-12 months+ Location:-San Jose , CA(Onsite - Work from Office 5 days per week). About the Role: We are seeking a highly skilled and motivated ASIC Design Verification Engineer with over 6 years of experience in the field of verification. As an Individual Contributor, he/she will play a crucial role in ensuring the quality and reliability of our cutting-edge ASIC designs, contributing to industry-leading innovations. Key Responsibilities: Dev

Design Verification EngineerJob Title - Design Verification Engineer

Innova Solutions, IncCompany Name - Innova Solutions, Inc

•

Remote or Mountain View, California, USA

Third Party, Contract

A client of Innova Solutions is looking for an Design Verification Engineer. Position type: Contract Duration: 12+ Months Location: Mountain View, CA (Onsite Job) As a Design Verification Engineer, you will need: Minimum Qualifications: Experience in SV and UVM and good debugging skills.Understanding of AMBA protocols.Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/co

Design Verification EngineerJob Title - Design Verification Engineer

Mindsource IncCompany Name - Mindsource Inc

•

Sunnyvale, California, USA

Contract

Title: Sr. Design Verification Engineer Location: Onsite - Sunnyvale, CA (or) Austin, TX Duration: Long-term Type: Contract (W2/C2C) Rate: $110-$115/hr Responsibilities: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause, and resol

Mixed-Signal Design Verification EngineerJob Title - Mixed-Signal Design Verification Engineer

Talent Junction, LLC.Company Name - Talent Junction, LLC.

•

San Jose, California, USA

Contract, Third Party

Title: Mixed-Signal Design Verification Engineer Location: San Jose, CA Key Technical Skills:UVM/System Verilog, Python, Synopsys/Cadence EDA Verifications Tools, AMS Verification Required Experience/Skills: Good knowledge of System-Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc. Good understanding of digital design for mixed signal control loops and designing Verilog / Verilog- A code to control analog circuits (e.g. bandgap, PLL, Amplifier, Filters

Design Verification Engineer || Mountain View, CA (Onsite)Job Title - Design Verification Engineer || Mountain View, CA (Onsite)

E-Solutions, Inc.Company Name - E-Solutions, Inc.

•

Mountain View, California, USA

Full-time

Job Role- Design Verification Engineer Location- Mountain View, CA (Onsite) Job Descriptions- Key Responsibilities: Strong understanding of SV and UVM and good debugging skills. Understanding of AMBA protocols. Understand design specs and develop test plans based on functional and architectural requirements Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing Develop directed and random testcases, perform coverage analysis, and close functional/code cover

Design Verification Engineer at Santa Clara, CA (Hybrid)Job Title - Design Verification Engineer at Santa Clara, CA (Hybrid)

Infobahn Softworld Inc.Company Name - Infobahn Softworld Inc.

•

Santa Clara, California, USA

Contract, Third Party

Role Title: Design Verification Engineer Location: Santa Clara, CA, 95054 (Hybrid 3 days a week) Duration: 12+ months contract Job Duties: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for an I/O SOC. Be part of a team of design verification team, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Candidate will be participating in the

Design Verification EngineerJob Title - Design Verification Engineer

Yoh - A Day & Zimmerman CompanyCompany Name - Yoh - A Day & Zimmerman Company

•

Remote or Santa Clara, California, USA

Full-time

Design Verification Engineer Scope: Design and development of the IO subsystems for a high-performance SoC from scratch, working closely with the Architecture and RTL teams. Develop detailed block-level design specifications and plans for a high-performance IO Subsystem. Create and implement reusable block-level components in SV, UVM, and C++, including microarchitectural models, monitors, and checkers. Develop and optimize the IO subsystem design to ensure functionality and performance are in a

Design Verification EngineerJob Title - Design Verification Engineer

Avance ConsultingCompany Name - Avance Consulting

•

Remote

Full-time

<>Key Responsibilities:Strong understanding of SV and UVM and good debugging skills.Understanding of AMBA protocols.Understand design specs and develop test plans based on functional and architectural requirementsBuild UVM/System Verilog-based verification environments for IP/subsystem/SoC level testingDevelop directed and random testcases, perform coverage analysis, and close functional/code coverageDebug simulation failures and work closely with RTL designers to resolve issuesExecute regressio

Design Verification EngineerJob Title - Design Verification Engineer

TecHobbitCompany Name - TecHobbit

•

Remote

Contract

Title: Design Verification Engineer Location: Remote Duration: 12 months with possible extension Requirement: Good Design Verification Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis &

Design Verification EngineerJob Title - Design Verification Engineer

JConnect IncCompany Name - JConnect Inc

•

San Jose, California, USA

Full-time

Role: Design Verification Engineers (SoC-5, PCIe-5)Location: Bay AreaSalary: 160-240k (DOE) Free health insurancePTOs: 10 Business days (Including sick leaves) Key Skills: UVM, SoC, PCIe, High Bandwidth memory, Emulation (Zebu or Palladium) Job Description: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from speci

Design Verification Engineer- Remote- USAJob Title - Design Verification Engineer- Remote- USA

Yochana IT SolutionsCompany Name - Yochana IT Solutions

•

Contract, Third Party

Good DV Skill with major GLS work experience. Expertise in testbench updates for GLS Expertise in Scripting languages perl or python Experience with Make, Yaml & Json file systems. Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis). Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows. Experience with flow optimizations such as Grey/Black-boxing techniques Good at communicating requirements/issues wit

Electrical Design Verification Test (EDVT) EngineerJob Title - Electrical Design Verification Test (EDVT) Engineer

Oxford Global ResourcesCompany Name - Oxford Global Resources

•

Sunnyvale, California, USA

Contract

Position Title: Electrical Design Verification Test (EDVT) Engineer Location: Sunnyvale, CA- 100% onsite Length of Contract: 6 months+ extensions (potential for conversion - Contract-to-perm) Background check Required Scope: 2-3 weeks to onboard, with a probable start date of early April timeframe. Looking for person can do Network Testing and DVT especially strong in EDVT with ability to understand reading EE schematics, and strong broad knowledge of hardware in addition to networking product

ASIC Engineer, Senior Staff, Physical Design VerificationJob Title - ASIC Engineer, Senior Staff, Physical Design Verification

Juniper NetworksCompany Name - Juniper Networks

•

Sunnyvale, California, USA

Full-time

At Juniper, we believe the network is the single greatest vehicle for knowledge, understanding, and human advancement the world has ever known. To achieve real outcomes, we know that experience is the most important requirement for networking teams and the people they serve. Delivering an experience-first, AI-Native Network pivots on the creativity and commitment of our people. It requires a consistent and committed practice, something we call the Juniper Way. Job Description for an ASIC Physi

Distinguish Engineer Design VerificationJob Title - Distinguish Engineer Design Verification

Marvell Semiconductor Inc.Company Name - Marvell Semiconductor Inc.

•

Santa Clara, California, USA

Full-time

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and be

ASIC Engineer (Design Verification)Job Title - ASIC Engineer (Design Verification)

CloudiousCompany Name - Cloudious

•

Sunnyvale, California, USA

Contract, Third Party

ASIC Engineer (Design Verification) Bay Area, CA or Austin, TX 12 Months Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collab

Asic Manager, Design VerificationJob Title - Asic Manager, Design Verification

Meta Platforms, Inc. (f/k/a Facebook, Inc.)Company Name - Meta Platforms, Inc. (f/k/a Facebook, Inc.)

•

Sunnyvale, California, USA

Full-time

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA Asic Manager, Design Verification: Work with researchers and architects defining verification plans for each of the different core IP. (ref. code REQ-2502-147199: $272,316/year - $287,650/year). Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus or equity or sales incentives, if a

ASIC Design EngineerJob Title - ASIC Design Engineer

Yochana IT SolutionsCompany Name - Yochana IT Solutions

•

Santa Clara, California, USA

Contract, Third Party

ASIC Design Engineer Location: Santa Clara, CA Onsite Contract Overview of the Role As an ASIC Design Engineer , you will play a crucial role in the development and optimization of our cutting-edge ASIC solutions. Your work will directly impact the efficiency, performance, and scalability of our products, driving forward the company's objectives and contributing to technological innovations that shape the industry. Detailed Responsibilities Run and manage Fusion Compiler, ICC II, and Innovus

RTL Design EngineerJob Title - RTL Design Engineer

Yoh - A Day & Zimmerman CompanyCompany Name - Yoh - A Day & Zimmerman Company

•

Santa Clara, California, USA

Full-time

RTL Design Engineer Looking for a solid RTL Design Engineer who has a strong background in supporting RISC-V houses. The primary technology will be focused around SOCs that are built around ML Accelerators. This person should have a solid background in RTL Design and also have an understanding of verification flows. This person should be a strong engineer and be able to come in and provide solid and consistent support with minimal hand holding or guidance. Required 7+ Years of RTL Design experi