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Principal Software Engineer, RTL Optimization Tools

NVIDIA Corporation

Santa Clara, California, USA

Full-time

NVIDIA's success builds on a foundation of industry leading hardware. A key strategy in achieving this is our combining of the best of external EDA with highly optimized, internal EDA tools. Our team develops these tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++. We are seeking an innovative CAD Software Engineer with particular interest in strategies and algorithms for large scale RTL quality, timing, and power optimization. Such optimization usuall

Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)

SpaceX

Irvine, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadban

SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)

SpaceX

Irvine, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband in

DFT Engineer

Broadcom Corporation

San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, t

ASIC Engineering Technical Lead- DFT

Cisco Systems, Inc.

San Jose, California, USA

Full-time

The application window is expected to close on 4/25/25 This is an onsite role and will require working out of the Milpitas/San Jose office Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way thr

SPE Head of Product Test and Package Eng

Ericsson Inc.

Remote or Austin, Texas, USA

Full-time

Grow with us About this Opportunity This position is in Austin, Texas and is not a remote opportunity. Ericsson Inc. does not sponsor US work authorizations for this job position including H-1B, O-1, and TN. Ericsson also does not hire F-1's working onfor this position. Are you ready for a ground floor opportunity with Ericsson as an ASIC Product Engineering Manager? If so, this is the place for you! The Ericsson Radio and Baseband Products have our ASICs as their backbone. Our ASICs continuo

Design for Test Engineer (DFT)

Yoh - A Day & Zimmerman Company

Remote or Austin, Texas, USA

Full-time

Design for Test Engineer (DFT) The role is Design for Test (DFT) for high-performance designs going into industry AI/ML architectures. This will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage & facilitating debug and yield learnings while minimizing design intrusions. Scope: Implementation of DFT features into RTL (using Verilog). Understand DFT Architectures & micro-archit