PLL Jobs in San Jose, CA

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Post Silicon validation Engineer

Comprehensive Resources Inc.

•

San Jose, California, USA

Full-time, Part-time, Contract, Third Party

PSV SOC Validation Engineer Location: San Jose,CA Experience: 10 years of experience Education: B.E/M. E in Electronics & Communication Engineering Lead the development and execution of bring-up and silicon validation test plans for the SoC. Perform validation of SoC peripherals including LPDDRx, PCIe, I2C, and qSPI. Manage and oversee all phases of the validation lifecycle, from initial bring-up to production release. Collaborate closely with cross-functional hardware and software teams to des
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Posted 1 day ago

Senior ASIC Clock Engineer

NVIDIA Corporation

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Remote or Santa Clara, California, USA

Full-time

NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on pe
Posted 11 days ago | Updated 9 hours ago

Clock Distribution Engineer, Dojo

Tesla Motors

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Palo Alto, California, USA

Full-time

The Dojo Hardware team is looking for a Clock Distribution Engineer to work in Palo Alto, CA. This Engineer will be responsible for the design and implementation of clocks at both the SOC and IP level. Responsibilities Design custom clock distribution from PLL to sub-blocks meeting low latency and jitter specs for various SOC clocks Write modular clock RTL to handle changes, integrating it into designStrong tcl knowledge to automate the clock tree generation based on bottoms-up load feedbackWor