PLL Jobs in San Jose, CA

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Senior ASIC Clock Engineer

NVIDIA Corporation

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Remote or Santa Clara, California, USA

Full-time

NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on pe
Posted 3 days ago | Updated 9 hours ago

System Signal/Power Integrity Engineer

Broadcom Corporation

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San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: System Signal/Power Integrity Engineer Responsibilities Support high data rate SerDes applications - up to 112Gbps NRZ and 224G PAM4 systemsSystem level Signal and Power Integrity design trade-offs and debugCollaborate with package, PCB, and silicon d
Posted 60+ days ago | Updated 10 hours ago

Clock Distribution Engineer, Dojo

Tesla Motors

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Palo Alto, California, USA

Full-time

The Dojo Hardware team is looking for a Clock Distribution Engineer to work in Palo Alto, CA. This Engineer will be responsible for the design and implementation of clocks at both the SOC and IP level. Responsibilities Design custom clock distribution from PLL to sub-blocks meeting low latency and jitter specs for various SOC clocks Write modular clock RTL to handle changes, integrating it into designStrong tcl knowledge to automate the clock tree generation based on bottoms-up load feedbackWor