Role: Memory PHY RTL design Engineer Location: Boxborough MA 01719 | Hybrid 3 days onsite per week Duration: 12+ months THE ROLE: The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologie
