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620 results (22 new)

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ASIC RTL Designer

Divit Technologies, Inc.

Remote • Today

Easy Apply

Contract

Depends on Experience

RTL Design Engineer

TetriQ Solutions LLC

California • Today

Easy Apply

Full-time

RTL Verification Engineer

VGAI Solutions Inc

Santa Clara, California • 8d ago

Easy Apply

Contract

65 - 70

Sr. ASIC/SoC Design verification Engineer

Mavensoft Technologies, LLC

Remote • 5d ago

Easy Apply

Contract

120 - 127

DFT (Design For Test) Lead - Remote Role

Avacend, Inc.

Remote • Today

Easy Apply

Contract

Depends on Experience

FPGA Engineer (with Secret Clearance)

Oxford Global Resources

Manchester, New Hampshire • 7d ago

Easy Apply

Contract

70 - 100

STA Engineer

Stellar IT Solutions

Austin, Texas • Today

Easy Apply

Full-time, Part-time, Contract, Third Party

Formal Verification Engineer

Experis

Santa Clara, California • Today

Full-time

Compensation information provided in the description

ASIC/SoC Verification Architect – Short Supplier

NR Consulting LLC

St. Louis, Missouri • 15d ago

Easy Apply

Contract

Up to 160

Firmware Engineer

Broadcom Corporation

Fort Collins, Colorado • Today

Full-time

USD 121,900.00 - 195,000.00 per year

Principal Product Engineer

Cadence Design Systems Inc

Austin, Texas • Today

Full-time

Design Verification Engineer – UVM/SystemVerilog

Avila IT

San Jose, California • Yesterday

Easy Apply

Contract

Depends on Experience

ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA)

Teradyne Incorporated

Reading, Massachusetts • Today

Full-time

USD 98,700.00 - 157,900.00 per year

CPU Core Verification Engineer

AMD (Advanced Micro Devices)

Fort Collins, Colorado • Today

Full-time

USD 126,700.00 per year

ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

Senior Serdes System Design Engineer/Architect

Broadcom Corporation

Austin, Texas • Today

Full-time

USD 143,800.00 - 230,000.00 per year

ASIC Timing and Methodology Engineer

Qualcomm Technologies

Tijuana, Baja California • Today

Full-time

CPU RTL Power Engineer

Qualcomm Technologies

Austin, Texas • Today

Full-time

USD 155,400.00 - 233,200.00 per year

ASIC Design Engineer II, Annapurna Labs - Cloud-Scale Machine Learning Acceleration

Annapurna Labs (U.S.) Inc.

Austin, Texas • Today

Full-time

SoC Debug Engineer, Staff

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 145,600.00 - 218,400.00 per year

SoC Debug Engineer, Senior Staff

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 174,400.00 - 261,600.00 per year

Junior Design Verification Engineer, Amazon Leo

Amazon Kuiper Manufacturing Enterprises LLC

Austin, Texas • Today

Full-time

SoC Power Design Engineer (Engineer - Staff Eng)

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 145,600.00 - 218,400.00 per year

Senior FPGA / RTL Design Engineer - Signal Processing

Motorola Solutions

Los Angeles, California • Today

Full-time

USD 155,000.00 - 195,000.00 per year

Principal Engineer, HIG-HBM Design

Micron Technology, Inc.

Richardson, Texas • Today

Full-time

EDA/CAD Software Engineer, Staff

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 145,600.00 - 218,400.00 per year

ASIC Engineer, Annapurna Labs

Amazon.com Services LLC

Austin, Texas • Today

Full-time

EDA/CAD SW Engineer

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 101,400.00 - 152,200.00 per year

EDA/CAD Software Engineer

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 101,400.00 - 152,200.00 per year

Hardware Engineer

IMC

Chicago, Illinois • 21d ago

Full-time

USD 200,000.00 - 225,000.00 per year

Divit Technologies, Inc.

Job Details

Skills

ASIC
AXI
Change Data Capture
Collaboration
DDR SDRAM
Debugging
GitHub
IP
IPS
Intellectual Property
Level Design
Physical Data Model
RTL
Scripting
Git
Management
PCI Express
SystemVerilog
Timing Closure
System On A Chip
Synopsys
Version Control
Python

Summary

Integrate and configure IPs using FlexNoC for AXI, DDR, PCIe, and other interconnect architectures.
Develop and refine microarchitecture and infrastructure components for SoC-level integration.
Write, optimize, and maintain SystemVerilog RTL for IP and top-level design.
Perform timing closure using Synopsys PrimeTime and ensure sign-off quality results.
Conduct synthesis using Synopsys Design Compiler, optimizing area, performance, and power.
Run and debug LINT and CDC checks to ensure high-quality, clean RTL.
Collaborate cross-functionally with design, verification, and physical design teams.
Develop automation scripts in Python to streamline design, build, and verification flows.
Manage version control and collaboration using Git/GitHub.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91165394
Position Id: 9114862
Posted 2 hours ago

Company Info

About Divit Technologies, Inc.

At Divit Technologies Inc., we integrate innovation with excellence to deliver custom IT solutions tailored to your business needs. As one of the premier provider, we specialize in AI, Automation, Data Science, DevSecOps, Quality Engineering, and IT Staffing Solutions. Our advanced technology ensures clients achieve unmatched efficiency, security, and growth through state-of-the-art, tailored solutions.

We streamline processes with IT Automation, transforming raw data into valuable insights with our Data Science services. Our DevSecOps solutions integrate security into development, while our Quality Engineering ensures software credibility and performance.

Our expert team offers comprehensive IT staffing solutions, matching top talent with top companies for permanent, contract, or project-based roles.

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Contact the job poster

Arun Kumar

Lead Technical Recruiter @ Divit Technologies, Inc.

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Remote jobs at Divit Technologies, Inc.

Divit Technologies, Inc.

Job Details

Skills

ASIC
AXI
Change Data Capture
Collaboration
DDR SDRAM
Debugging
GitHub
IP
IPS
Intellectual Property
Level Design
Physical Data Model
RTL
Scripting
Git
Management
PCI Express
SystemVerilog
Timing Closure
System On A Chip
Synopsys
Version Control
Python

Summary

Integrate and configure IPs using FlexNoC for AXI, DDR, PCIe, and other interconnect architectures.
Develop and refine microarchitecture and infrastructure components for SoC-level integration.
Write, optimize, and maintain SystemVerilog RTL for IP and top-level design.
Perform timing closure using Synopsys PrimeTime and ensure sign-off quality results.
Conduct synthesis using Synopsys Design Compiler, optimizing area, performance, and power.
Run and debug LINT and CDC checks to ensure high-quality, clean RTL.
Collaborate cross-functionally with design, verification, and physical design teams.
Develop automation scripts in Python to streamline design, build, and verification flows.
Manage version control and collaboration using Git/GitHub.

Dice Id: 91165394
Position Id: 9114862
Posted 2 hours ago