ASIC RTL Designer
Divit Technologies, Inc.
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Job Details
Skills
- ASIC
- AXI
- Change Data Capture
- Collaboration
- DDR SDRAM
- Debugging
- GitHub
- IP
- IPS
- Intellectual Property
- Level Design
- Physical Data Model
- RTL
- Scripting
- Git
- Management
- PCI Express
- SystemVerilog
- Timing Closure
- System On A Chip
- Synopsys
- Version Control
- Python
Summary
- Integrate and configure IPs using FlexNoC for AXI, DDR, PCIe, and other interconnect architectures.
- Develop and refine microarchitecture and infrastructure components for SoC-level integration.
- Write, optimize, and maintain SystemVerilog RTL for IP and top-level design.
- Perform timing closure using Synopsys PrimeTime and ensure sign-off quality results.
- Conduct synthesis using Synopsys Design Compiler, optimizing area, performance, and power.
- Run and debug LINT and CDC checks to ensure high-quality, clean RTL.
- Collaborate cross-functionally with design, verification, and physical design teams.
- Develop automation scripts in Python to streamline design, build, and verification flows.
- Manage version control and collaboration using Git/GitHub.
- Dice Id: 91165394
- Position Id: 9114862
- Posted 1 hour ago
Company Info
At Divit Technologies Inc., we integrate innovation with excellence to deliver custom IT solutions tailored to your business needs. As one of the premier provider, we specialize in AI, Automation, Data Science, DevSecOps, Quality Engineering, and IT Staffing Solutions. Our advanced technology ensures clients achieve unmatched efficiency, security, and growth through state-of-the-art, tailored solutions.
We streamline processes with IT Automation, transforming raw data into valuable insights with our Data Science services. Our DevSecOps solutions integrate security into development, while our Quality Engineering ensures software credibility and performance.
Our expert team offers comprehensive IT staffing solutions, matching top talent with top companies for permanent, contract, or project-based roles.