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Design Verification Lead

AIT Global, Inc.

San Jose, California • Today

Easy Apply

Contract, Third Party

Design Verification (DV) Lead

Carman Solutions Group

Sunnyvale, California • Today

Easy Apply

Full-time

Depends on Experience

Verification Lead Memory Controller (CHI-G / DFI)

AIT Global, Inc.

San Jose, California • Today

Easy Apply

Contract, Third Party

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

AIT Global, Inc.

San Jose, California • Today

Easy Apply

Third Party, Contract

Design Verification Engineer III

BCforward

Sunnyvale, California • Today

Easy Apply

Contract

$65.32 - $65.32 per hour

ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead)

Boeing Company

Mountain View, California • Today

Full-time

USD 98,600.00 - 133,400.00 per year

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)

AIT Global, Inc.

San Jose, California • Today

Easy Apply

Contract, Third Party

Senior Staff Engineer, GPU Design Verification (Formal Verification)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 198,200.00 - 297,200.00 per year

Senior Staff Engineer, GPU Design Verification (Subsystems)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 180,200.00 - 297,200.00 per year

ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV

Boeing Company

Mountain View, California • Today

Full-time

USD 164,900.00 - 223,100.00 per year

Verification Lead Memory Controller

Comprehensive Resources Inc.

San Jose, California • Yesterday

Easy Apply

Full-time, Part-time, Contract, Third Party

Opening for Design Verification Engineer, Principal - CA

Aptuity Solutions, Inc

Santa Clara, California • Today

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Full-time

$180,000 - $310,000

Design Verification (DV) Engineer

VentureSoft Global

Sunnyvale, California • 14d ago

Easy Apply

Contract, Third Party

Depends on Experience

SoC Design Verification Engineer

E-Solutions, Inc.

San Jose, California • 12d ago

Easy Apply

Full-time, Third Party

Depends on Experience

Design Verification Engineer

HCP ONE LLC

San Jose, California • 27d ago

Easy Apply

Contract

Depends on Experience

2027 Masters Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 104,000.00 per year

2027 Undergrad Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 66,560.00 per year

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

Comprehensive Resources Inc.

San Jose, California • Yesterday

Easy Apply

Full-time, Part-time, Third Party, Contract

Verification Lead Memory Controller (CHI-G / DFI)

ChaTeck Incorporated

San Jose, California • 6d ago

Easy Apply

Contract, Third Party

Depends on Experience

Principal Engineer, Design Verification - DDR Memory Subsystems

Altera Corp.

San Jose, California • Today

Full-time

USD 209,500.00 - 299,200.00 per year

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

ChaTeck Incorporated

San Jose, California • 6d ago

Easy Apply

Contract, Third Party

Depends on Experience

Lead Verification Engineer / Principal Verification Engineer – PCIe Gen5/Gen6

Delton Solutions LLC

San Jose, California • Today

Easy Apply

Contract, Third Party

55 - 60

Verification Engineer - Aeromechanical (Design & Test)

Pivotal

Palo Alto, California • Today

Full-time

USD 115,000.00 - 145,000.00 per year

Manufacturing Test Design Lead

OSI Engineering, Inc.

Hybrid in Cupertino, California • 4d ago

Easy Apply

Contract

80 - 105

Product Design Engineering Lead - Beats

Apple, Inc.

Cupertino, California • Today

Full-time

Principal/Lead Design Engineer(Onsite)

Stellent IT LLC

San Jose, California • Today

Easy Apply

Contract, Third Party

Staff Mechanical Engineer - Spacecraft Mechanical Design Technical Lead

Muon Space

San Jose, California • Today

Full-time

USD 202,000.00 - 223,000.00 per year

Employee Listening Design & Delivery Lead

Kforce Technology Staffing

Remote or Mountain View, California • Today

Contract

$80 - $95 hourly

Principal/Lead Design Engineer Memory Controller (CHI-G / DFI)

StoneGate-Technologies LLC

San Jose, California • Yesterday

Easy Apply

Contract, Third Party

Up to $60

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)

ChaTeck Incorporated

San Jose, California • 6d ago

Easy Apply

Contract, Third Party

Depends on Experience

Job Details

Skills

python
shell scripting
Perl
Questa
Xcelium

Summary

Job Title: Design Verification Lead
Location: San Jose/Portland USA

Position Summary:

We are looking for a highly motivated Design Verification Lead with strong expertise in SystemVerilog/UVM-based verification of complex memory subsystems. The candidate will be responsible for driving verification of high-performance memory architectures involving AXI4 interconnects, HBM interfaces, buffer management schemes, transaction scheduling, and high-throughput data movement engines.

The ideal candidate should have extensive experience in subsystem-level verification, verification closure, performance validation, and debugging of complex scenarios involving a large number of concurrent outstanding memory transactions.

Key Responsibilities:

Lead verification activities for memory-intensive SoC subsystems and AI accelerator architectures.
Develop comprehensive verification plans, test strategies, and coverage models.
Architect and implement reusable SystemVerilog/UVM verification environments
Verify complex AXI4-based subsystems including:
Multi-master/multi-slave configurations
Outstanding transaction handling
Out-of-order completions
QoS and arbitration mechanisms
Bandwidth and latency validation
Verify HBM memory interfaces and high-bandwidth memory access traffic patterns.
Develop stimulus and checkers to validate:
Large numbers of pending memory transactions
Read/write ordering
Backpressure handling
Buffer overflow/underflow conditions
Performance corner cases
Verify memory buffer management algorithms and data movement engines.
Validate optimized scheduling and arbitration logic for throughput, fairness, and latency requirements.
Develop protocol compliance checkers, scoreboards, assertions, and functional coverage models.
Drive regression execution, failure analysis, coverage closure, and verification signoff.
Collaborate closely with Architecture, RTL Design, Performance Modeling, Firmware, and Validation teams.

Required Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Minimum 8+ years of Design Verification experience in ASIC/SoC development.

Strong expertise in:

SystemVerilog
UVM
Assertions (SVA)
Coverage-Driven Verification
Constrained Random Verification
Extensive hands-on experience building UVM environments from scratch.
Strong subsystem-level verification experience.
Deep understanding of AXI4 protocol including:
Outstanding transactions
ID-based ordering
Bursts
Interleaving
Performance validation
Protocol compliance checking
Experience verifying memory subsystems involving:
Memory controllers
DMA engines
Buffer managers
Data movement architecture
Good understanding of HBM architecture and interfaces.
Experience verifying high-throughput memory access patterns with large numbers of concurrent pending transactions.
Experience validating schedulers, arbitration logic, and traffic management algorithms.
Strong debugging and root-cause analysis skills.

Preferred Qualifications:

Experience with HBM2E / HBM3 / HBM3E memory subsystems.
Experience in AI/ML accelerator, networking, or datacenter SoCs.
Knowledge of cache-coherent interconnects and memory hierarchies.
Experience with performance modeling and verification.
Experience with Formal Verification and Assertions.
Experience with Emulation/FPGA acceleration platforms.
Familiarity with Python, Perl, or Shell scripting for automation.

Desired Technical Skills:

SystemVerilog
UVM
AXI4 / AXI4-Stream
HBM2E / HBM3
Memory Controllers
DMA Engines
Buffer Management
Scheduler Verification
Functional Coverage
Assertions (SVA)
VCS / Xcelium / Questa
Python Scripting

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10106248
Position Id: 2026-4409
Posted 5 hours ago

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Similar Jobs

Design Verification Engineer

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Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s

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Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

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Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

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Verification Lead Memory Controller

San Jose, California

•

Yesterday

Verification Lead - Memory Controller (CHI-G / DFI) Location: San Jose, CA Department: Hardware / Design Verification Level: Lead Experience: 10+ Years Job Overview We are seeking an experienced Verification Lead to own the verification strategy, planning, and execution for a Memory Controller subsystem, with strong expertise in ARM CHI-G and DFI interface verification. The ideal candidate will lead a team of verification engineers, drive coverage closure and regression, and ensure sign-off

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SoC Design Verification Engineer

San Jose, California

•

12d ago

Position Title: SoC Design Verification Engineer Location: San Jose, CA Remote/Onsite: Onsite Types of Hire: Fulltime Job Description: - We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets. Key Responsibilities: Develop and execute S

Easy Apply

Full-time, Third Party

Depends on Experience

Job Details

Skills

python
shell scripting
Perl
Questa
Xcelium

Summary

Job Title: Design Verification Lead
Location: San Jose/Portland USA

Position Summary:

Key Responsibilities:

Lead verification activities for memory-intensive SoC subsystems and AI accelerator architectures.
Develop comprehensive verification plans, test strategies, and coverage models.
Architect and implement reusable SystemVerilog/UVM verification environments
Verify complex AXI4-based subsystems including:
Multi-master/multi-slave configurations
Outstanding transaction handling
Out-of-order completions
QoS and arbitration mechanisms
Bandwidth and latency validation
Verify HBM memory interfaces and high-bandwidth memory access traffic patterns.
Develop stimulus and checkers to validate:
Large numbers of pending memory transactions
Read/write ordering
Backpressure handling
Buffer overflow/underflow conditions
Performance corner cases
Verify memory buffer management algorithms and data movement engines.
Validate optimized scheduling and arbitration logic for throughput, fairness, and latency requirements.
Develop protocol compliance checkers, scoreboards, assertions, and functional coverage models.
Drive regression execution, failure analysis, coverage closure, and verification signoff.
Collaborate closely with Architecture, RTL Design, Performance Modeling, Firmware, and Validation teams.

Required Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Minimum 8+ years of Design Verification experience in ASIC/SoC development.

Strong expertise in:

SystemVerilog
UVM
Assertions (SVA)
Coverage-Driven Verification
Constrained Random Verification
Extensive hands-on experience building UVM environments from scratch.
Strong subsystem-level verification experience.
Deep understanding of AXI4 protocol including:
Outstanding transactions
ID-based ordering
Bursts
Interleaving
Performance validation
Protocol compliance checking
Experience verifying memory subsystems involving:
Memory controllers
DMA engines
Buffer managers
Data movement architecture
Good understanding of HBM architecture and interfaces.
Experience verifying high-throughput memory access patterns with large numbers of concurrent pending transactions.
Experience validating schedulers, arbitration logic, and traffic management algorithms.
Strong debugging and root-cause analysis skills.

Preferred Qualifications:

Experience with HBM2E / HBM3 / HBM3E memory subsystems.
Experience in AI/ML accelerator, networking, or datacenter SoCs.
Knowledge of cache-coherent interconnects and memory hierarchies.
Experience with performance modeling and verification.
Experience with Formal Verification and Assertions.
Experience with Emulation/FPGA acceleration platforms.
Familiarity with Python, Perl, or Shell scripting for automation.

Desired Technical Skills:

SystemVerilog
UVM
AXI4 / AXI4-Stream
HBM2E / HBM3
Memory Controllers
DMA Engines
Buffer Management
Scheduler Verification
Functional Coverage
Assertions (SVA)
VCS / Xcelium / Questa
Python Scripting

Dice Id: 10106248
Position Id: 2026-4409
Posted 5 hours ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Design Verification Engineer

San Jose, California

•

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Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

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Verification Lead Memory Controller

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SoC Design Verification Engineer

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