Lead Verification Engineer / Principal Verification Engineer – PCIe Gen5/Gen6

Job Title: Lead Verification Engineer / Principal Verification Engineer – PCIe Gen5/Gen6
Location: San Jose, CA
Experience: 10+ years

Position Summary
We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transaction Layer, Controller, PHY and Serdes. The candidate will be responsible for verification planning, methodology definition, UVM environment architecture, coverage closure, protocol compliance verification, and leadership of a team of verification engineers.
The ideal candidate should possess deep expertise in PCIe protocol, Transaction/Data Link/Physical Layers, LTSSM, PHY/SerDes interactions, UVM methodology, assertions, formal verification, emulation, and post-silicon debug support. The role requires close collaboration with Architecture, RTL Design, DFT, Firmware, Physical Design, and Validation teams.

Key Responsibilities

·       Verification Ownership

·       Own complete verification signoff for PCIe Gen5/Gen6 Controller and Subsystem.

·       Develop overall verification strategy and execution plan.

·       Drive verification activities from specification review through tape-out.

·       Review architecture, microarchitecture, and RTL specifications.

·       Define verification metrics and signoff criteria.

·       Create comprehensive verification plans covering:

·       Transaction Layer, Physical Layer, PIPE, and Data Link Layer

·       SR-IOV supporting large virtual functions.

·       Recovery Mechanisms

Map every protocol feature to:

·       Testcases, Assertion, Functional Coverage and Scoreboards.

·       Architect reusable UVM verification environments.

·       Build subsystem- and SoC-level verification environments.

·       Enable reuse from IP to subsystem to SoC verification.

·       Define coverage architecture.

Drive:

·       Functional Coverage

·       Code Coverage

·       Assertion Coverage

·       Cross Coverage

·       Analyze coverage holes and drive closure.

·       Establish signoff methodology and metrics.

·       Verify Controller-to-PHY integration.

·       Verify PIPE interface compliance.

Validate:

·       Equalization sequences

·       Link training

·       Recovery behavior

·       Speed changes

·       Lane width changes

·       Work closely with PHY and Analog teams.

Leadership Responsibilities

·       Lead and mentor verification engineers.

·       Perform verification reviews and audits.

·       Drive schedule planning and execution tracking.

·       Interface with customers and program management.

·       Own verification signoff reviews.