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San Jose, California

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Today

Immediate need for a talented Senior Design Verification Engineer . This is a Fulltime opportunity with long-term potential and is located in San Jose, CA(Onsite). Please review the job description below and contact me ASAP if you are interested. Job ID:26-19462 Pay Range: $150000 - $160000/annum. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibilities: Design and develo

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Full-time

$150,000 - $160,000

Senior Design Verification Engineer-Need local To CA

Sunnyvale, California

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11d ago

Role: Senior Design Verification Engineer Location -Sunnyvale, CA-Onsite No of Positions - 2 Exp needed - 8 to 10 yrs Duration - Longterm Here is the JD: Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause, and res

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Contract, Third Party

$70 - $80

Design Verification Engineer - Ethernet

Santa Clara, California

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20d ago

Design Verification Engineer Overview Upscale AI is developing next-generation Ethernet networking infrastructure optimized for large-scale AI and GPU cluster environments. We are seeking experienced Design Verification Engineers with strong networking and ASIC verification backgrounds to help validate high-performance networking silicon and AI fabric technologies. ResponsibilitiesDevelop and execute verification plans for networking ASICs and SoC designsBuild and maintain SystemVerilog/UVM-base

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Full-time

USD180000 - USD300000 per annum, Benefits: $180k-$300k Annual Salary

Design Verification Engineer

Santa Clara, California

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28d ago

No Contract Only Fulltime Title: Design Verification Engineer Loc: Santa Clara CA(Weekly 5 days onsite) Type: Fulltime Key Responsibilities: DV Engineer with strong expertise in SystemVerilog, UVM, and AMBA protocols. Experienced in building IP/SoC testbenches, writing test plans from design specs, and closing functional/code coverage. Skilled in power-aware (UPF/CPF) simulations, debugging RTL failures, and collaborating across DFT, PD, and post-silicon teams to ensure high-quality design de

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Full-time

Depends on Experience

Design Verification Engineer - San Jose, CA – Onsite - Contract Role

San Jose, California

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19d ago

Job description: We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. Key responsibilitiesEnd to end ownersh

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Contract, Third Party

Depends on Experience

Design Verification Engineer

Remote

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12d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

Depends on Experience

RTL Design Engineer / Design Verification Engineer

Remote

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Yesterday

R-069895 RTL Design Engineer Wireless SoC (Remote PST) Location: Remote (must be aligned with PST time zone / willing to work PST hours) We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon. Required Skills 5+ years of hands-on RTL design experience (

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Full-time, Third Party

Depends on Experience

Senior Staff Engineer, Design Verification

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 134,390.00 - 201,300.00 per year

Sr Staff Electronic Design Verification Test (EDVT Engineer Hardware

Santa Clara, California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 143,100.00 - 231,475.00 per year

Staff/Principal Engineer - Design Verification (SoC expert/lead)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: ASIC Design Verification SoC Lead (Technical lead role) Position Description: This is a position for lead member in Micron's ASIC Verification and Emulation group.

Full-time

USD 168,000.00 - 336,000.00 per year

Staff Engineer, Design Verification

Santa Clara, California

•

Today

Full-time

USD 113,920.00 - 170,600.00 per year

Principal Engineer, GPU Design Verification (Subsystems)

San Jose, California

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Today

Position Summary Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy - the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the wo

Full-time

USD 221,700.00 - 364,800.00 per year

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

Hardware Design Verification/Test Engineer

San Jose, California

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7d ago

Position: Hardware Design Verification/Test Engineer Location: San Jose, CA - Onsite Roles & Responsibilities: Participate on a project team of engineers involved in hardware development and testing.Define system-level Design Verification Test procedures.Perform complex system-level unit and integration testing.Debug and mitigate complex system-level issues.Collaborate with hardware design, software/diagnostic, and manufacturing test engineers to develop and execute product test strategies.Deve

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Contract

Depends on Experience

Sr Memory Subsystem Verification Engineer

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 145,600.00 per year

Senior Debug Verification Engineer

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 149,100.00 - 215,000.00 per year

Staff Engineer, ASIC Design Verification

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

ASIC / SoC RTL Design Engineer

San Jose, California

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Today

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS SoC design using ARM, PCIe, DDR, and Ethernet. Responsibilities: Architecture definition and micro-specs RTL coding, verification, and debug Synthesis, timing closure, and bring-up Requirements: ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,

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Contract

$60 - $62.50 per hour

Design Engineer 4

Newark, California

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15d ago

Job Title: Engineering & IT - Design Engineer 4 Start/End Dates: 25/05/2026 - 31/12/2026 Candidate Location Requirements: Newark, California, Engineer, Exterior Trim We are currently seeking an Exterior Trim Engineer. This position requires a responsibility for designing and developing parts of the exterior systems of a world class vehicle in terms of both styling and function. Our ideal candidate exhibits a can-do attitude and approaches his or her work with vigor and determination. Candidates

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Contract, Third Party

Depends on Experience

Hardware Design Engineering, Senior Director - Active Electric Cable / Smart Cable Module Business

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

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