DESIGN VERIFICATION ENGINEER

Sunnyvale, CA, US • Posted 14 hours ago • Updated 14 hours ago
Full Time
No Travel Required
On-site
Depends on Experience
Fitment

Dice Job Match Score™

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Job Details

Skills

  • System Verilog
  • UVM/OVM
  • Verilog

Summary

Hiring: Design Verification Engineer

Location: Sunnyvale, CA 94086 (Onsite)
Full-Time | W2 Only
Interview: Webcam

Client: META

We are seeking an experienced Design Verification Engineer with 10+ years of experience and strong expertise in System Verilog, UVM/OVM, and Verilog. The ideal candidate should have hands-on experience in IP, Sub-system, and SoC-level verification of complex digital designs, along with strong skills in functional verification, testbench development, debugging, and coverage-driven verification.

Complete job details will be shared directly with the consultant.

 

If you have any questions, feel free to reach out via email. We look forward to your response.

 

Regards,

Madhu

(445) (400) (2863) (No calls please)

madhu at sunrayinformatics dot com

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10430719
  • Position Id: 9136900
  • Posted 14 hours ago
Contact the job poster
MV

Madhu Veluri

Recruiter @ SUNRAY INFORMATICS

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