Sunnyvale, California
•
2d ago
TITLE: SR DESIGN VERIFICATION ENGINEER LOCAITON: SUNNYVALE,CA (ONSITE) FULL TIME Senior Design Verification Engineer with 10+ years of experience who has strong hands-on expertise in SystemVerilog, UVM, Verilog, and digital design verification. The candidate should be capable of developing verification plans and testbenches, performing IP/SoC-level verification, debugging design issues, and driving functional and code coverage to closure. Experience with Python/Perl scripting and EDA tools is re
Easy Apply
Full-time
Depends on Experience



