DESIGN VERIFICATION ENGINER _ FULLTIME

TITLE: SR DESIGN VERIFICATION ENGINEER

LOCAITON: SUNNYVALE,CA (ONSITE)

FULL TIME

Senior Design Verification Engineer with 10+ years of experience who has strong hands-on expertise in SystemVerilog, UVM, Verilog, and digital design verification. The candidate should be capable of developing verification plans and testbenches, performing IP/SoC-level verification, debugging design issues, and driving functional and code coverage to closure. Experience with Python/Perl scripting and EDA tools is required. Exposure to AI/ML, Networking, Video, ARM/RISC-V, or Data Center designs is an added advantage.

Mandatory Skills:

• Verilog, SystemVerilog

• UVM/OVM methodology

• IP/Sub-system/SoC verification

• Testbench development and functional verification

• Functional and code coverage

• Debugging and root-cause analysis

• EDA tools and Python/Perl/Shell scripting

  BEST REG

  NAVEEN

  )

  EMAIL(:) NAVEEN AT SUNRAYINFORMATICS DOT COM