Design Verification Engineer (UVM)

Job Title: Design Verification Engineer (UVM)

Location: Sunnyvale, CA (onsite)

Mandatory Skill: Strong hands-on UVM expertise is a MUST.

Key Responsibilities

• Develop and maintain reusable UVM-based verification environments.
• Create and implement test plans, test scenarios, and verification strategies.
• Develop constrained-random and directed test cases using SystemVerilog.
• Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards.
• Develop assertions using SystemVerilog Assertions (SVA).
• Perform functional, code, and assertion coverage analysis.
• Debug simulation failures and identify design or testbench issues.
• Work closely with RTL designers and architecture teams to understand design specifications.
• Drive functional coverage closure and achieve verification sign-off.
• Participate in design reviews, verification planning, and regression analysis.
• Automate verification tasks using scripting languages such as Python, Perl, or Shell.

Required Skills

• Strong hands-on experience in UVM-based functional verification.
• Excellent knowledge of SystemVerilog.
• Experience developing reusable UVM testbenches from scratch.
• Strong understanding of OOP concepts and constrained-random verification.
• Experience with UVM sequences, sequencers, drivers, monitors, agents, and scoreboards.
• Hands-on experience with SystemVerilog Assertions (SVA).
• Knowledge of functional coverage and code coverage.
• Experience with simulation and debugging tools such as:
  • Synopsys VCS
  • Cadence Xcelium
  • Siemens Questa
• Strong debugging and problem-solving skills.
• Good understanding of digital design concepts and RTL verification methodologies.

Regards

Shubham Shehrawat