Design Verification Engineer

Hi Associate,

Greetings for the day,

We have a position as a Design Verification Engineer role in San Jose, CA. Please find the job description below for this position.

Role: Design Verification Engineer

Location: San Jose, CA (Hybrid)

Duration: 24 Months

Required Skills:

• Demonstrated expertise in developing and implementing advanced verification environments using Universal Verification Methodology (UVM) for complex digital designs.
• Strong proficiency in C programming language for developing test benches, reference models, and verification utilities within a robust verification framework.

Preferred Skills:

• Familiarity with scripting languages such as Python or Perl for automation of verification flows and data analysis is highly advantageous.
• Experience with formal verification techniques and tools to complement simulation-based verification efforts would be beneficial.

Additional Skills:

• Proven ability to contribute to the architectural definition of verification methodologies and infrastructure improvements.
• Strong understanding of digital design principles, computer architecture, and hardware/software co-verification concepts.

Job Responsibilities:

• Design and implement advanced verification environments for complex digital designs using Universal Verification Methodology (UVM).
• Develop comprehensive test plans and verification strategies to ensure functional correctness and coverage for various IP blocks and sub-systems.
• Lead the creation of reusable verification components, including UVM agents, sequences, and functional models, to enhance verification efficiency.
• Execute verification campaigns, debug failures, and analyze coverage metrics to achieve tape-out quality for ASIC or SoC designs.
• Contribute to the architectural definition of verification methodologies and infrastructure improvements to support future projects.
• Collaborate closely with design engineers to understand specifications, identify potential design issues, and drive timely resolutions.
• Mentor junior verification engineers on best practices, UVM methodology, and effective debugging techniques to foster team growth.
• Develop and maintain C-based reference models and test benches for co-simulation and validation of hardware-software interfaces.
• Drive the adoption of advanced verification techniques such as formal verification and assertion-based verification to improve verification completeness.
• Optimize verification flows and tools to improve efficiency, reduce simulation time, and enhance overall productivity.
• Ensure adherence to industry standards and internal quality processes throughout the entire verification lifecycle.
• Participate in design reviews and provide critical feedback on design for testability and verifiability.
• Take ownership of specific verification blocks or sub-systems, ensuring their thorough validation and sign-off.

Thanks & Regards

RAJU REDDY |Sr. Team Manager

CIS Technology Inc

Plano, TX 75074

Direct: