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Digital Verification Engineer

Neuralink

South San Francisco, California • Today

Full-time

USD 131,000.00 - 243,000.00 per year

PCIe Verification Engineer

TekLeaders, Inc

Remote or San Francisco, California • Today

Easy Apply

Full-time, Part-time, Contract, Third Party

Sr. FPGA Verification Engineer

Reliable Robotics

Remote or Mountain View, California • Today

Full-time

USD 215,000.00 - 300,000.00 per year

Mixed-Signal Verification Engineer

Apple, Inc.

San Francisco, California • Today

Full-time

Sr Software Verification Engineer

Globus Medical

Redwood City, California • Today

Full-time

ASIC Verification Engineer

Pyramid Technology Solutions, Inc.

Remote • Yesterday

Easy Apply

Contract

Depends on Experience

ASIC Verification Engineer

Oxford Global Resources

Hybrid in Burlingame, California • Today

Easy Apply

Contract

$80 - $90

Software Engineer, Verifications Platform

Upstart

Remote • Today

Full-time

USD 142,000.00 - 196,600.00 per year

Job Details

Skills

Business Intelligence
Recovery
CPU
System On A Chip
Art
Interfaces
FOCUS
Digital Signal Processing
ASIC
Scripting
Python
Perl
Makefile
Tcl
Unix
Shell
Code Coverage
Regression Analysis
RTL
Physical Data Model
Testing
Integrated Circuit
Modeling
SystemVerilog
SystemC
C++
Formal Verification
UVM
ARM
AMBA
FPGA
Emulation
Writing
Debugging
Training
Insurance
PPO

Summary

About Neuralink:

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Job Description & Responsibilities:

We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers a rare and unique opportunity to have a high impact in realizing state-of-the-art brain-computer interfaces. The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP) . We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Key qualifications:

Minimum 3 years of experience in digital ASIC verification.
Excellence in SystemVerilog.
Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
Experience with code coverage and regression setup.

Preferred qualifications:

Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
Experience on building test benches, testing, and debugging for a complex system-on-chip.
Experience in formal verification.
Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
Experience with IEEE-1801 (UPF) based design simulation flows
Experience with low power gate level simulations
Exposure with low power formal verification flows
Strong hands-on experience in verification methodologies such as UVM
Knowledge of ARM/RISC-V processor, AMBA bus
Knowledge of power aware verification
Experience with FPGA/emulation
Experience with lab system bring up, writing diagnostic, and lab debugging

Expected Compensation:

The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees.

Base Salary Range:

$131,000-$243,000 USD

What We Offer:

Full-time employees are eligible for the following benefits listed below.

An opportunity to change the world and work with some of the smartest and most talented experts from different fields
Growth potential; we rapidly advance team members who have an outsized impact
Excellent medical, dental, and vision insurance through a PPO plan
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs) *Temporary Employees & Interns excluded
401(k) plan *Interns initially excluded until they work 1,000 hours
Parental leave *Temporary Employees & Interns excluded
Flexible time off *Temporary Employees & Interns excluded

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: RTX1d0651
Position Id: b6b56e47fc77e51a44a096deb1f38155
Posted 9 hours ago

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Senior ASIC Verification Engineer

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At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software developmen

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Principal Engineer, Digital Verification and Emulation

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Senior Verification Engineer

Mountain View, California

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Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and complian

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Verification Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is focused on enabling customers to develop products with a sustainable and substantial competitive advantage. APD does this by delivering best in class technology platforms, easy to integrate bleeding edge intell

Full-time

USD 121,900.00 - 195,000.00 per year

Job Details

Skills

Business Intelligence
Recovery
CPU
System On A Chip
Art
Interfaces
FOCUS
Digital Signal Processing
ASIC
Scripting
Python
Perl
Makefile
Tcl
Unix
Shell
Code Coverage
Regression Analysis
RTL
Physical Data Model
Testing
Integrated Circuit
Modeling
SystemVerilog
SystemC
C++
Formal Verification
UVM
ARM
AMBA
FPGA
Emulation
Writing
Debugging
Training
Insurance
PPO

Summary

Minimum 3 years of experience in digital ASIC verification.
Excellence in SystemVerilog.
Experience in developing automation flow and scripts such as Python, Perl, Makefile, Tcl and UNIX shell
Experience with code coverage and regression setup.

Preferred qualifications:

Experience working on complex digital systems from architecture, microarchitecture, RTL, verification and physical design using industry standard tools.
Experience on building test benches, testing, and debugging for a complex system-on-chip.
Experience in formal verification.
Functional modeling experience and logic verification with SystemVerilog, SystemC/C++.
Experience with IEEE-1801 (UPF) based design simulation flows
Experience with low power gate level simulations
Exposure with low power formal verification flows
Strong hands-on experience in verification methodologies such as UVM
Knowledge of ARM/RISC-V processor, AMBA bus
Knowledge of power aware verification
Experience with FPGA/emulation
Experience with lab system bring up, writing diagnostic, and lab debugging

An opportunity to change the world and work with some of the smartest and most talented experts from different fields
Growth potential; we rapidly advance team members who have an outsized impact
Excellent medical, dental, and vision insurance through a PPO plan
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs) *Temporary Employees & Interns excluded
401(k) plan *Interns initially excluded until they work 1,000 hours
Parental leave *Temporary Employees & Interns excluded
Flexible time off *Temporary Employees & Interns excluded

Dice Id: RTX1d0651
Position Id: b6b56e47fc77e51a44a096deb1f38155
Posted 9 hours ago

Fitment

Dice Job Match Score™

🤯 Applying directly to the forehead...

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Senior ASIC Verification Engineer

San Francisco, California

•

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Full-time

Principal Engineer, Digital Verification and Emulation

San Jose, California

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Full-time

USD 190,000.00 - 250,000.00 per year

Senior Verification Engineer

Mountain View, California

•

Today

Full-time

USD 119,800.00 - 234,700.00 per year

Verification Engineer

San Jose, California

•

Today

Full-time

USD 121,900.00 - 195,000.00 per year