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Design Verification Engineer

Inabia Software & Consulting Inc.

San Jose, California • 4d ago

Easy Apply

Third Party, Contract

Depends on Experience

DESIGN VERIFICATION ENGINEER

SUNRAY INFORMATICS

Sunnyvale, California • Today

Easy Apply

Full-time

Depends on Experience

Design Verification Engineer

Reveille Technologies

San Jose, California • 2d ago

Easy Apply

Full-time

Depends on Experience

Design Verification Engineer

SIGNin Solutions Inc.

San Jose, California • 5d ago

Easy Apply

Full-time, Third Party

Depends on Experience

Formal Design Verification Engineer

NUBYT, INC.

San Jose, California • 6d ago

Easy Apply

Contract, Third Party

85 - 95

GPU Design Verification Engineer

Qualcomm

Santa Clara, California • Today

Full-time

Compensation information provided in the description

ASIC Design Verification Engineer - W2 Contract

XFORIA Inc

Menlo Park, California • 2d ago

Easy Apply

Contract

Depends on Experience

DV (Design Verification) Engineer (California, Texas) - W2 Only

Collaborate Solutions, Inc.

San Jose, California • 5d ago

Easy Apply

Full-time

$60 - $70

DESIGN VERIFICATION ENGINER _ FULLTIME

SUNRAY INFORMATICS

Sunnyvale, California • 2d ago

Easy Apply

Full-time

Depends on Experience

Design Verification Engineer

MSH Group

Remote • 2d ago

Easy Apply

Contract

40 - 50

Senior Lead Engineer - Design Verification

Altera Corp.

San Jose, California • Today

Full-time

USD 231,500.00 - 330,000.00 per year

Mechanical Design Engineer

AgreeYa Solutions

Milpitas, California • 3d ago

Easy Apply

Contract

65 - 70

Engineering Intern - Design Verification, Neural Engine (Spring 2027 Co-op)

Rivian

Palo Alto, California • Today

Full-time

USD 45.00 - 51.00 per hour

Physical Design Engineer

Cystems Logic

Sunnyvale, California • 10d ago

Easy Apply

Contract, Third Party

SR PHYSICAL DESIGN ENGINEER _ FULL TIME

SUNRAY INFORMATICS

Sunnyvale, California • 2d ago

Easy Apply

Full-time

Depends on Experience

Creo Mechanical Design Engineer # 26-28112

U.S. Tech Solutions Inc.

Milpitas, California • 3d ago

Easy Apply

Contract

$70 - $73

Principal Verification Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 230,000.00 per year

Senior Debug Verification Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Senior Staff Pre Silicon Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

ASIC Design/SDC Engineer

Inabia Software & Consulting Inc.

San Jose, California • 4d ago

Easy Apply

Contract, Third Party

Depends on Experience

Pre-Silicon Digital Verification Engineer

Apple, Inc.

Sunnyvale, California • Today

Full-time

IC Verification Engineer

Broadcom Corporation

San Jose, California • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Verification Engineer ASIC/CPU/GPU Functional Verification

VGAI Solutions Inc

San Jose, California • 4d ago

Easy Apply

Contract

75 - 80

Verification Engineer 4

Black Rock Group

San Jose, California • 12d ago

Easy Apply

Contract, Third Party

Depends on Experience

2027 Masters Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 104,000.00 per year

2027 Undergrad Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 66,560.00 per year

Senior Physical Verification CAD Engineer

Microsoft Corporation

Mountain View, California • Today

Full-time

USD 119,800.00 - 234,700.00 per year

Formal Verification Engineer - #26-21752

U.S. Tech Solutions Inc.

Ben Lomond, California • 16d ago

Easy Apply

Contract

$80 - $85

RTL Verification Engineer # 26-21738

U.S. Tech Solutions Inc.

Ben Lomond, California • 23d ago

Easy Apply

Contract

$80 - $85

Industrial Design Engineer 3

DGN Technologies

Sunnyvale, California • 2d ago

Easy Apply

Third Party, Contract

$103 - $103

Job Details

Skills

ASIC
IPS
NOC
PCI Express
Perl
Reporting
Ethernet
SystemVerilog
UVM
SV
PCIe
HBM
Design Verification Engineer

Summary

We are seeking Design Verification Engineer with exposure on Developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)

Key Skill: SV/UVM, PCIe/Ethernet/HBM

What You'll Be Doing:

Strong in SV/UVM scale test bench

AXI expertise, NOC/Crossbar, Performance

Regression/Triage and coverage closure

Need asap → Program has already started and is in execution

Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less documentation available

What we are looking for:

A bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline.

Verification closure with team

Make/Perl/Python

Ensure customer satisfaction.

Reporting to customer on daily or weekly progress effectively

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10337997
Position Id: 9133713
Posted 4 days ago

Fitment

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Contact the job poster

Adhunika Sharma

Recruiter @ Inabia Software & Consulting Inc.

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Design Verification Engineer

San Jose, California

•

5d ago

Client: Etched Design Verification Engineer 6 Openings Location: San Jose, CA & Austin, TX - onsite Please find the JD: Job Summary We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ab

Easy Apply

Full-time, Third Party

Depends on Experience

IC Verification Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Responsibilities: Architect and develop scalable and reusable Testbench environment using the framework of Verification Methodologies.Drive Test plans for all features for Block/Core/SOC and Write Functional coverage for these features.Build pseudo-ran

Full-time

USD 143,800.00 - 230,000.00 per year

ASIC Design Verification Engineer - W2 Contract

Menlo Park, California

•

2d ago

Job Details ASIC Design Verification Engineer 12+ Months Contract with Possible Extension Austin, TX & Menlo park, CA Job Summary We are seeking a highly motivated ASIC Design Verification Engineer to join our silicon engineering team. The ideal candidate will have strong experience in SystemVerilog/UVM-based verification of complex IPs or SoCs and will be responsible for developing test cases, debugging RTL issues, and driving coverage closure. Responsibilities Maintain reusable SystemVerilog/U

Easy Apply

Contract

Depends on Experience

Senior Debug Verification Engineer

San Jose, California

•

Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 149,100.00 - 215,000.00 per year

More jobs at Inabia Software & Consulting Inc. in San Jose, CA

Job Details

Skills

ASIC
IPS
NOC
PCI Express
Perl
Reporting
Ethernet
SystemVerilog
UVM
SV
PCIe
HBM
Design Verification Engineer

Summary

We are seeking Design Verification Engineer with exposure on Developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)

Key Skill: SV/UVM, PCIe/Ethernet/HBM

What You'll Be Doing:

Strong in SV/UVM scale test bench

AXI expertise, NOC/Crossbar, Performance

Regression/Triage and coverage closure

Need asap → Program has already started and is in execution

Ability to work on Amazon tools, flows, methodology. Work is in start-up mode with less documentation available

What we are looking for:

Verification closure with team

Make/Perl/Python

Ensure customer satisfaction.

Reporting to customer on daily or weekly progress effectively

Dice Id: 10337997
Position Id: 9133713
Posted 4 days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Contact the job poster

Adhunika Sharma

Recruiter @ Inabia Software & Consulting Inc.

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Design Verification Engineer

San Jose, California

•

5d ago

Easy Apply

Full-time, Third Party

Depends on Experience

IC Verification Engineer

San Jose, California

•

Today

Full-time

USD 143,800.00 - 230,000.00 per year

ASIC Design Verification Engineer - W2 Contract

Menlo Park, California

•

2d ago

Easy Apply

Contract

Depends on Experience

Senior Debug Verification Engineer

San Jose, California

•

Today

Full-time

USD 149,100.00 - 215,000.00 per year

More jobs at Inabia Software & Consulting Inc. in San Jose, CA