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Sunnyvale, California

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Today

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA Design Verification Engineer: Collaborates with researchers, architects, and designers to establish comprehensive verification strategies for a variety of core IP blocks and complex System-on-Chip (SoC) solutions. (ref. code REQ-2602-159167: $136,926/year to $162,580/year). Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect th

Full-time

Depends on Experience

VLSI Design Verification Engineer In San Jose, CA

San Jose, California

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Today

Role: Senior/Staff VLSI Engineer Ethernet FEC DV Duration: 12+ Months Location: San Jose, CA || Onsite Role Job Description-: We are seeking a highly skilled and motivated VLSI Design Verification Engineer with deep expertise in Forward Error Correction (FEC) and Ethernet protocols. In this role, you will own the verification of advanced FEC IP cores (RS-FEC, KR/KP4, or next-gen) within high-speed Ethernet controllers (25G/50G/100G/200G/400G+). You will develop sophisticated UVM environments, d

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Contract

Depends on Experience

GPU Design Verification Engineer

San Jose, California

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28d ago

Job Title: GPU Design Verification Engineer Location: San Jose, CA (Onsite) Duration: 6+ months (Contract) with the possibility of extension Job Description: We are seeking a highly skilled Design Verification Engineer to join our team at Samsung SARC/ACL. The successful candidate will be responsible for verifying the functionality and performance of our cutting-edge GPU designs. Your primary focus will be on developing and executing verification plans, creating testbenches, and debugging compl

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Contract

$80 - $90

Design Verification Engineer (GPU)

San Jose, California

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4d ago

Job Title: "Design Verification Engineer (GPU)" Location: San Jose, CA (Onsite, 5 days a week) Duration: Long Term Description As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date I UVM version will place you among

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Contract

Depends on Experience

FPGA Design/Verification Engineer

Sunnyvale, California

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Today

Location: Sunnyvale, CA Salary: $90.00 USD Hourly - $100.00 USD Hourly Description: Job Title: FPGA Design/Verification Engineer Duration: 6+ Months (Possible Extension) Location: Sunnyvale, CA, Possible: onsite Denver CO. Job Description: The selected candidate will be responsible for ASIC & FPGA verification on R&D program. This engineer will be a verification UVM expert. This engineer with have experience: -Verifying FPGA and/or ASIC designs including creating UVM verification environ

Contract

Compensation information provided in the description

Digital Design Verification Engineer

San Jose, California

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17d ago

JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, Cadence tools Xcelium, Windows based tools.

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Contract

Depends on Experience

Principal Design Verification Engineer (NPU)

Hybrid in Mountain View, California

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Today

Project Description: The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role is responsible for driving the verification excellence of state-of-the-art Neural Processing Unit (NPU), including the development of comprehensive testbenches and vali

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Contract

$80 - $90

Design Verification Engineer

San Jose, California

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4d ago

Role: Design Verification Engineer Location: San Jose CA/ Irvine CA / San Diego CA Job Description:Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simula

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Full-time

Depends on Experience

Principal Engineer, Design Verification (NPU)

Hybrid in Mountain View, California

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18d ago

Title: Principal Engineer, Design Verification (NPU) Location: Mountain View, California -Hybrid Occasional travel may be required, less than 5% Project Description: The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role is responsible for dri

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Contract

Depends on Experience

Design Verification Engineer

Remote or Toronto, Ontario

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6d ago

RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge of Verilog/SystemVerilog/UVM Strong programming skills including object-oriented programming Working experience with digital logic design and verification Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems Demonstrates good analysis, problem-solving, and critical thinking skills Effective interpersonal, teamwork, and communication skills

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Contract

Depends on Experience

Senior Design Verification Engineer

Remote

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11d ago

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

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Contract

90 - 105

Senior Design Verification Engineer

Remote

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12d ago

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Contract

90 - 100

ASIC Engineer, Design Verification

Sunnyvale, California

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5d ago

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA ASIC Engineer, Design Verification: Develop functional tests based on verification test plan. (ref. code REQ-2512-158352: $186,000/year to $192,170/year) Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus or equity or sales incentives, if applicable. In addition to base salary, Me

Full-time

Depends on Experience

Lead - SoC/Sub-System Design Verification

Sunnyvale, California

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11d ago

Job Title: Lead SoC/Sub-System Design Verification Location: Sunnyvale, CA (Onsite) Job Summary:We are seeking an experienced and highly motivated Lead Engineer to drive the design verification of complex System-on-Chip (SoC) and sub-system architectures. The ideal candidate will lead a team of verification engineers, define verification strategies, and ensure the delivery of high-quality silicon through comprehensive verification planning, execution, and closure. Key Responsibilities: Lead the

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Contract, Third Party

Depends on Experience

Design Verification Lead

Sunnyvale, California

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Today

Role: Design Verification Lead Location: Sunnyvale onsite Job Type: Contract Interview: Phone/Video Job Description: Experience: 12+ Years Role: Lead - SoC/Sub-System Design Verification About the Role We are seeking an experienced Design Verification Lead to drive SoC-level verification strategy, lead high performing teams, and ensure first time right silicon. This role requires deep technical expertise, strong leadership, and the ability to influence cross functional teams while workin

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Contract, Third Party

USD DOE

CPU Verification Engineer (Multiple Locations)

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role and Responsibilities Work with CPU and SOC Architects to understand the concepts an

Full-time

USD 167,100.00 - 250,700.00 per year

Sr. ASIC/SOC Verification Engineer (Silicon Engineering)

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the

Full-time

USD 170,000.00 - 230,000.00 per year

CPU Verification Engineer (RISC-V)

Santa Clara, California

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Today

Full-time

USD 167,100.00 - 250,700.00 per year

Early Career Talent - Media Tribology Design Engineer

San Jose, California

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Today

Company Description At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we've been doing just that-our technology helped people put a man on the moon and capture the first-ever picture of a black hole. We offer an expansive portfolio of technologies, HDDs

Full-time

USD 140,300.00 per year

Mechanical Design Engineer (Tooling Design Focus)

Santa Clara, California

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11d ago

Title: Mechanical Design Engineer (Tooling Design Focus) Location: Santa Clara, CA 100% onsite Length of Contract: 6-12 months (Potential Contract-to-hire based on performance) Process: 3 rounds, Phone/Onsite Ideal Start Date: ASAP Background Check/Drug Screen Scope: As a Mechanical Design Engineer focused on tooling, you ll collaborate with a cross-functional team of Hardware Engineering, Platform Design, Reliability Engineering, and global Contract Manufacturing (CM) partners. You ll be part

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Contract

$60 - $70

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