Remote or Redmond, Washington
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Today
job summary: Join a team dedicated to designing analog mixed-signal IPs for high-performance data center processors. This is an exceptional opportunity for an experienced Layout Engineer to focus on full-custom physical layout and verification using the most advanced CMOS nodes, including FinFET and gate-all-around (2-3nm). You will be instrumental in optimizing circuit design for performance, area, and power, contributing to cutting-edge technology that is rare and highly valued in the industr
Contract
USD59 - USD62