Responsibilities:
· Develop test structure layouts using design automation by SKILL coding in Cadence Virtuoso Design Environment
· Develop/own parametrized cells (Pcells) to assist the layout design automation
· Develop/own SKILL based scripts for PNR (place & route) routing automation
· Interpret design rules & macro specifications, and collaborating with broader team engineers to achieve the desired structure layouts while ensuring that designed layouts pass Design Rule Checks (DRC).
· Close and frequent cooperation with development engineers from interdisciplinary teams will be required for this dynamic team environment.
Required professional and technical expertise:
· Bachelor or above Degree in Electrical Engineering, Computer Engineering, Physics Engineering or related field with experience in VLSI chip development or semiconductor technology
· Experiences with Cadence SKILL programming language and/or related languages (Python and/or Perl, etc), at least 3 years.
· Familiarity with layout verification tools from Cadence Pegasus, Synopsys ICV, or Siemens Calibre, including design rule checking (DRC) with 3+ years of relevant experience
· Capability of using SKILL and/or Python and/or Perl to create design automation infrastructure tools and to aid the layout design automation
· Strong understanding of Linux environments and shell scripting with a minimum of 2+ years of experience
· Strong understanding of physical layout and technology ground rules
· Ability to debug errors and solve problems in a team environment
· Strong communication & Interpersonal skills
Preferred Professional and technical expertise:
• Strong experience using the Cadence Virtuoso layout design tool, at least 5 years
• Experiences with Cadence SKILL programming language for Pcell Development & Design Automation, at least 3 years
• Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g., GitHub, GitLab, or Bitbucket)
• Experienced user of Synopsys ICV DRC checking tool
• Experience with advanced sub-micron semiconductor technology nodes
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