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San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, throug

Full-time

USD 141,300.00 - 226,000.00 per year

Sr DFT Engineer

Santa Clara, California

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3d ago

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

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Third Party, Contract

Depends on Experience

Senior DFT Engineer (Need Local to CA)

Santa Clara, California

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6d ago

Senior DFT Engineer [ATPG, MBIST, IO Test, Clock Verification]Client- ConfidentialLocation: Santa Clara, CAOnsiteExperience: 4+ Years in DFT Job SummaryWe are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The e

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Contract

$70 - $90

Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification]

Santa Clara, California

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7d ago

JobTitle:SeniorDFTEngineer[ATPG,MBIST,IOTest,ClockVerification] Location:SantaClara,CA Experience:4+YearsinDFT JobSummary WeareseekinganexperiencedSeniorDFT/ATPGEngineertosupportNVIDIAshighperformanceGPUandSoCdesigns.TherolefocusesondeliveringrobustDesignforTestability(DFT)solutions,comprehensiveATPG,andadvancedtestfeaturessuchasMBIST,IOTest,andClockVerification,ensuringhighcoverage,yield,andsiliconreliability.TheengineerwillworkcloselywithNVIDIAscrossfunctionalteamstoenablefirsttimerightsilico

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Contract

Depends on Experience

DFT Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)

Full-time

USD 81,000.00 - 130,000.00 per year

Senior ASIC Design Engineer - Clocks IP

Santa Clara, California

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Today

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human

Full-time

USD 136,000.00 - 218,500.00 per year

ASIC Test Engineer

San Jose, California

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11d ago

We are looking for a highly experienced ASIC Test Engineer to join our clients Product Engineering team and drive end-to-end ASIC test development from prototype to high-volume production. Job Title: ASIC Test Engineer Location: San Jose, CA, relocation assistance provided Type: Full time with Client Overview We are seeking an experienced ASIC Test Engineer to support the industrialization of new semiconductor products. This role is part of the Product Engineering team within the unit an

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Full-time, Third Party

Depends on Experience

ASIC Physical Design Engineer

San Jose, California

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10d ago

Candidates must be currently authorized to work in the United States on a full-time, permanent basis. StaffRight Associates and our clients do not provide visa sponsorship for this position. PLEASE DO NOT APPLY IF YOU DO NOT MEET THESE ABOVE QUALIFICATIONS Great base pay, bonus, terrific benefits and exceptional 401k! he MissionStaffRight Associates is recruiting to identify a high-caliber ASICPhysical Design Engineer to spearhead the structural realization of next-generation System-on-Chip (So

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Full-time

170000 - 220000

Senior ASIC DV Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification e

Full-time

USD 127,100.00 - 226,000.00 per year

Product Planning Engineer-ASIC/SoC

San Jose, California

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Today

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Full-time

USD 140,000.00 per year

Staff/Principal Engineer. ASIC Design Verification (DDR expert)

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Position Title: Staff/Principal ASIC SoC Design Verification Engineer - DDR expert (Technical role) Position Description: This is a position for Staff technical member of Micron's

Full-time

USD 168,000.00 - 336,000.00 per year

Principal ASIC Engineer

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Play a key role in architecture and development of advanced verification environments for complex SoC components, while ensuring on time, one time best-in-class quality. Work in the field of Semico

Full-time

USD 233,157.00 - 336,000.00 per year

ASIC Verification Engineer

Saratoga, California

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Today

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Full-time

USD 140,000.00 - 200,000.00 per year

Verification Engineer - FPGA/ASIC

San Jose, California

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Today

Full-time

USD 124,040.00 per year

Senior Staff Firmware Engineer - low-level firmware/software for advanced Compute, Storage, and Custom ASIC platforms.

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 131,010.00 - 196,300.00 per year

Senior System ASIC Engineer - Speed and Reliability

Santa Clara, California

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Today

Join NVIDIA, a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency, and innovation. From our roots as a groundbreaking graphic company, we have evolved into a global leader in artificial intelligence, continuously pushing the boundaries to tackle complex challenges across diverse industries. Silicon Solutions Group (SSG) is a multifaceted, multi-functional team at NVIDIA. We sit at the crossroads of design, architecture, marketing, and productization. Ou

Full-time

USD 136,000.00 - 218,500.00 per year

CPU DFT Engineer

Santa Clara, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you?ll insure it becomes reality. We?re doing a ground up implementation of a new chip architecture, so you?ll have to ability

Full-time

Compensation information provided in the description

Principal Firmware Engineer - high-speed optical interconnects /custom silicon/ASIC design / microcontroller architectures /

Santa Clara, California

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Today

Full-time

USD 154,680.00 - 231,700.00 per year

Senior DFT Engineer

Santa Clara, California

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7d ago

Key Responsibilities Architect, implement, and validateDFT solutionsto improve controllability and observability in complex GPU/SoC designsLeadscan-based DFT implementation, including scan insertion, compression, and test logic integrationDevelop and debugATPG patternstargeting stuckat, transition, and additional fault modelsImplement and supportMBIST architecturesfor onchip memory test, diagnosis, and coverage improvementPerformIO Test planning and validationto ensure reliable interface and pin

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Contract, Third Party

Depends on Experience

DFT Engineers - Multiple roles

San Jose, California

•

Today

Job Detail :- Required Skills & Qualifications 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification co

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Full-time

Depends on Experience

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