Design For Test (DFT) Engineer

Job Description

Onsite San Jose - 5 days a week

Description
The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips.
Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.

JOB RESPONSIBILITIES:
Experience with memory BIST - Siemens Tessent Flow
Experience with gate-level simulation and simulation debug
Experience with automation and scripting - Tcl/Perl/Python
Experience with scan compression - SEQ/Ultra/TestKompress
Experience with ATPG - Tetramax
Experience with ATPG diagnosis, ATE debug and silicon bring up
DFT pattern translation - VTRAN
Experience with RTL design - Verilog/system Verilog
Some experience with STA and timing analysis concepts - PrimeTime (CDC, clock gating checks, timing constraints)

REQUIRED SKILLS AND EXPERIENCE:
5+ years relevant industrial DFT experience
Excellent problem solving and debugging skills
Ability to complete assignments independently