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Design Verification Engineer – UVM/SystemVerilog

Avila IT

San Jose, California • Today

Easy Apply

Contract

Depends on Experience

ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV

Boeing Company

Mountain View, California • Today

Full-time

USD 164,900.00 - 223,100.00 per year

ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead)

Boeing Company

Mountain View, California • Today

Full-time

USD 98,600.00 - 133,400.00 per year

ASIC Verification Engineer (UVM & GLS Focus)

Talent Groups

Remote • Today

Easy Apply

Contract

60 - 65

Senior Staff Engineer, GPU Design Verification (Subsystems)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 180,200.00 - 297,200.00 per year

Design Verification Engineer

SIGNin Solutions Inc.

San Jose, California • Today

Easy Apply

Full-time, Third Party

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Saim Technologies

Remote • Today

Easy Apply

Contract

70+

ASIC Verification Engineer (UVM & GLS Focus)

Metalight Solutions Inc

Remote • Today

Easy Apply

Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Talent Groups

Remote • Today

Easy Apply

Contract

Depends on Experience

Sr. ASIC/SoC Design verification Engineer

Mavensoft Technologies, LLC

Remote • 4d ago

Easy Apply

Contract

120 - 127

Mixed Signal Verification Engineer

Xoriant Corporation

San Jose, California • 14d ago

Easy Apply

Contract

90 - 150

Mixed Signal Verification Engineer _San Jose, CA (Onsite, Only local Candidates)

Xoriant Corporation

San Jose, California • Yesterday

Easy Apply

Contract

120 - 150

Verification Engineer

Stellent IT LLC

San Jose, California • Today

Easy Apply

Full-time

IC Verification Engineer

Broadcom Corporation

San Jose, California • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Senior Debug Verification Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Design Engineer III

West Coast Consulting LLC

Sunnyvale, California • Today

Contract

USD 80.00 - 86.00 per hour

Senior Staff Pre Silicon Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Principal Verification Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 230,000.00 per year

Lead IP Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Applications Engineering, Sr Engineer

Synopsys, Inc.

Sunnyvale, California • 27d ago

Full-time

Sr Solutions Engineer-FPGA/PCIe

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

DFX Engineer

Reveille Technologies

Sunnyvale, California • Today

Easy Apply

Contract

Depends on Experience

Staff Systems Design Engineer

Analog Devices, Inc.

San Jose, California • Today

Full-time

USD 150,978.00 - 218,624.00 per year

2027 Undergrad Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 66,560.00 per year

2027 Masters Hardware Design Verification Engineering Co-op/Intern

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 104,000.00 per year

IP Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 145,600.00 per year

Principal Emulation Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 207,000.00 - 230,000.00 per year

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Marvell Semiconductor Inc.

Santa Clara, California • Today

Full-time

USD 127,630.00 - 191,200.00 per year

PCIe Silicon Validation & Debug Engineer (x2)

Judge Group, Inc.

Sunnyvale, California • Today

Contract

USD 60.00 - 65.00 per hour

Product Architectural Model Development Leader

Altera Corp.

San Jose, California • Today

Full-time

USD 231,500.00 - 341,075.00 per year

Job Details

Skills

Design Verification
Design Verification Engineer
SystemVerilog
UVM
Functional Verification
IP Verification
PCIe
Ethernet
AXI
AMBA
ARM
ARC CPU
SoC Verification
IP Integration
VIP Integration
Functional Coverage
Coverage Closure
Constrained Random Verification
Testbench Development
RTL Debugging
Regression Testing
Verification Planning
Semiconductor
ASIC Verification
Hardware Verification.

Summary

Job Summary

We are seeking an experienced Design Verification (DV) Engineer to join our Interface IP Design Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog and UVM-based verification, along with expertise in validating complex IP subsystems and standard interface protocols. You will collaborate closely with architects, RTL designers, integration teams, and external IP vendors to ensure functional correctness, performance, and compliance with architectural specifications across the hardware-software stack.

Key Responsibilities

Own end-to-end design verification for one or more IP subsystems, including PCIe, Ethernet, ARM/ARC CPUs, low-power peripherals, and sensors.
Develop, maintain, and enhance reusable verification environments using SystemVerilog and UVM.
Understand vendor IP configurations, specifications, and integration requirements while coordinating with internal IP teams and external vendors.
Verify functional correctness, performance, protocol compliance, and corner-case scenarios.
Collaborate with SoC Design Verification and integration teams to ensure seamless integration of third-party IPs into the overall chip architecture.
Develop and execute verification plans, test scenarios, and regression suites.
Drive functional and code coverage closure, analyze verification gaps, and support final verification sign-off.
Debug complex failures, identify root causes, and work closely with RTL design and software teams to resolve issues.
Communicate verification progress, technical findings, risks, and recommendations to cross-functional stakeholders.

Required Qualifications

5+ years of hands-on experience in Design Verification Engineering.
Strong proficiency in SystemVerilog and UVM methodologies.
Experience developing scalable, reusable testbenches and constrained-random verification environments.
Familiarity with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPUs.
Experience with functional coverage, coverage analysis, regression testing, and verification sign-off.
Strong debugging, problem-solving, and analytical skills.
Ability to work independently, take ownership of verification tasks, and deliver results with minimal supervision.
Excellent communication and collaboration skills when working with design, architecture, integration, and software teams.

Preferred Qualifications

Experience working with external IP vendors and managing IP/VIP integration.
Hands-on experience with UVM-based verification and SystemVerilog testbench development.
Knowledge of SoC integration and hardware-software interaction.
Experience identifying corner-case bugs and debugging complex IP-level issues.
Ability to thrive in a fast-paced engineering environment and manage multiple verification priorities.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: RTX1ca0d4
Position Id: 9113699
Posted 5 hours ago

Fitment

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Contact the job poster

Navya Amsha

Recruiter @ Avila IT

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Job Details

Skills

Design Verification
Design Verification Engineer
SystemVerilog
UVM
Functional Verification
IP Verification
PCIe
Ethernet
AXI
AMBA
ARM
ARC CPU
SoC Verification
IP Integration
VIP Integration
Functional Coverage
Coverage Closure
Constrained Random Verification
Testbench Development
RTL Debugging
Regression Testing
Verification Planning
Semiconductor
ASIC Verification
Hardware Verification.

Summary

Job Summary

Key Responsibilities

Own end-to-end design verification for one or more IP subsystems, including PCIe, Ethernet, ARM/ARC CPUs, low-power peripherals, and sensors.
Develop, maintain, and enhance reusable verification environments using SystemVerilog and UVM.
Understand vendor IP configurations, specifications, and integration requirements while coordinating with internal IP teams and external vendors.
Verify functional correctness, performance, protocol compliance, and corner-case scenarios.
Collaborate with SoC Design Verification and integration teams to ensure seamless integration of third-party IPs into the overall chip architecture.
Develop and execute verification plans, test scenarios, and regression suites.
Drive functional and code coverage closure, analyze verification gaps, and support final verification sign-off.
Debug complex failures, identify root causes, and work closely with RTL design and software teams to resolve issues.
Communicate verification progress, technical findings, risks, and recommendations to cross-functional stakeholders.

Required Qualifications

5+ years of hands-on experience in Design Verification Engineering.
Strong proficiency in SystemVerilog and UVM methodologies.
Experience developing scalable, reusable testbenches and constrained-random verification environments.
Familiarity with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPUs.
Experience with functional coverage, coverage analysis, regression testing, and verification sign-off.
Strong debugging, problem-solving, and analytical skills.
Ability to work independently, take ownership of verification tasks, and deliver results with minimal supervision.
Excellent communication and collaboration skills when working with design, architecture, integration, and software teams.

Preferred Qualifications

Experience working with external IP vendors and managing IP/VIP integration.
Hands-on experience with UVM-based verification and SystemVerilog testbench development.
Knowledge of SoC integration and hardware-software interaction.
Experience identifying corner-case bugs and debugging complex IP-level issues.
Ability to thrive in a fast-paced engineering environment and manage multiple verification priorities.

Dice Id: RTX1ca0d4
Position Id: 9113699
Posted 5 hours ago

Fitment