Design verification Engineer

Role: Principal Engineer, Design Verification (NPU) Location: Mountain View, CA (Onsite) Job Type: Contract Project description The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role is responsible for driving the verification excelle

Job Title: Silicon Validation Engineer Location: Mountain View, CA Experince: 7+ Years Visa: Any Visa No OPT/CPT & GC''s on C2C. Job Responsibilities: Run and maintain silicon system regressions Report results of silicon system regressions Triage issues with various debugging tools Review and validate any system updates made by other teams Skills: Expertise in Python, C, and C++ Some knowledge of Verilog Attention to detail; analytical and problem-solving ability Education/Experience:

Position: FPGA Verification Engineer Location: San Jose, CA - Onsite Job Description & Responsibilities Own verification of entire FPGA design used in high-end router productsUnderstand design specifications and interact with design engineers to identify verification scenariosCreate test plans, constrained-random verification environments, test cases, regressions, and coverage reportsIdentify and write all types of coverage measures for stimulus and corner-casesQualifications Strong academic ba

FPGA Design Verification EngineerIntroduction:The FPGA Design Verification Engineer will play a crucial role in the team, leading FPGA design verification activities for advanced wireless communication systems. They will be responsible for developing, implementing, and validating DSP algorithms and functional blocks, contributing to phased array and beamforming projects, and ensuring high performance and reliability in FPGA-based systems. Responsibilities:Extensive experience in FPGA design and