Physical Design Engineer

Sunnyvale, CA, US • Posted 12 hours ago • Updated 12 hours ago
Full Time
On-site
Depends on Experience
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Cadence
  • Synopsys
  • Investor Relations
  • VLSI
  • RTL
  • Scripting
  • Static Timing Analysis
  • Python
  • Perl
  • Timing Closure

Summary

Only Local independent candidates are allowed to apply for this Role.

Location: Sunnyvale, CA | Austin, TX Experience: 10+ years

Brief: Lead RTL-to-GDSII implementation for high-performance SoCs on 3nm/5nm nodes. Focus on PnR, timing closure, and power integrity.

Core Tech Stack:

  • Tools: Cadence Innovus or Synopsys ICC2/Fusion Compiler.

  • Sign-off: PrimeTime (STA), RedHawk/Voltus (Power), Calibre (PV).

  • Scripting: Python, Tcl, or Perl.

Requirements:

  • Proven track record with FinFET (5nm or below).

  • Expert in STA, CTS, and EM/IR analysis.

  • BS/MS in Electrical Engineering or VLSI.
    Thanks and Regards,

    Praveenkumar

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10121364
  • Position Id: 8969781
  • Posted 12 hours ago
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