Physical Design Engineer

Mountain View, CA, US • Posted 30+ days ago • Updated 5 days ago
Full Time
On-site
Depends on Experience
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Cadence
  • Synopsys
  • Investor Relations
  • VLSI
  • RTL
  • Scripting
  • Static Timing Analysis
  • Python
  • Perl
  • Timing Closure
  • VSLI
  • ASIC
  • Electrical Engineering
  • EDA
  • EMIR
  • Electronic Engineering
  • Fusion
  • ICC
  • Design Optimization
  • Data Analysis
  • Ansys

Summary

Only Local independent candidates are allowed to apply for this Role.

Location: Mountainview, CA  

Core Technical Skills

  • ASIC Implementation: Full RTL-to-GDSII flow, Block-level Place & Route (PnR), Floorplanning, Power Planning, Placement, and Routing.

  • Timing & Signoff: Clock Tree Synthesis (CTS), Static Timing Analysis (STA), Timing Constraints (SDC), and Timing Closure (Setup/Hold/Transition/Noise).

  • Design Optimization: Power-Performance-Area (PPA) optimization, low-power design techniques, and EMIR (Electromigration & IR Drop) analysis.

EDA Tool Suite Proficiency

  • Synopsys: Fusion Compiler, ICC2, PrimeTime

  • Cadence / Ansys: Innovus (Optional), RedHawk, Voltus

Target Experience

  • Experience with advanced technology nodes (7nm / 5nm / 3nm).

  • Bachelor's or Master's degree in Electrical or Electronics Engineering.

Thanks and Regards,

Praveenkumar


Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10121364
  • Position Id: 8969781
  • Posted 30+ days ago
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PK

Praveen Kumar

Recruiter @ Reveille Technologies
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