Hardware Design Engineer

We are seeking an experienced Hardware Design and Failure Analysis Engineer with 10+ years of expertise in hardware engineering, board design, system-level debugging, and component-level failure analysis.

Key Responsibilities

• Design, debug, and troubleshoot complex hardware systems and board-level issues.
• Analyze high-speed interfaces, including PCIe Gen4/5/6, DDR4/DDR5, HBM, SerDes, and optical transceivers.
• Diagnose power integrity and signal integrity issues, including VRM transient droop, power distribution networks, PMBSVID telemetry, and switching noise.
• Lead root cause analysis and component-level physical failure analysis with silicon suppliers and external laboratories.
• Present technical findings and corrective actions to engineering leaders, cross-functional teams, and enterprise customers.
• Support hardware reliability, quality improvement, and system-level failure investigations.

Required Skills

• 10+ years of experience in hardware engineering, board design, or system-level failure analysis.
• Strong knowledge of PCIe, DDR, HBM, high-speed SerDes, and modern hardware architectures.
• Hands-on experience with power integrity, signal integrity, VRM debugging, and hardware root cause analysis.
• Experience coordinating component-level failure analysis with suppliers and analytical laboratories.
• Excellent technical communication, problem-solving, and stakeholder management skills.

Preferred Qualifications

• Experience supporting hyperscale cloud hardware environments such as Microsoft, Meta, Google, or AWS.
• Knowledge of chiplets, 2.5D/3D IC packaging, CoWoS, and silicon failure mechanisms.
• Python or C scripting experience for hardware automation and reproducing intermittent failures.

Work Arrangement: Candidates must be available to work onsite in San Jose, CA.