PCIe verification Engineer

Role: PCIe Verification Engineer Position Type: Contract Location: San Jose, CA Or Silver Lake, CA ( Day One Onsite) Job Description: Experience: 7+ Years Education: Bachelor/Master of Engineering (B.E./B.Tech/MS) in Electronics, Electrical, Computer Engineering, or a related field Role Summary: Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4, Gen5, and Gen6 specifications. Utilizing SystemVerilog and UVM, you will ensure robust protocol compl

Salary Verbias for San Jose, CA: GlobalLogic estimates the starting pay range for this role to be performed within the USA to be $135K to $155K and reflects base salary only and does not include additional performance-linked variable compensation, benefits etc that may be applicable for the role. This pay range is provided as a good faith estimate and the amount offered may be higher or lower. GlobalLogic takes many factors into consideration in making an offer, including candidate qualification

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the wo

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi