San Jose, California
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Today
Title: - Test Engineer Location: - San Jose, CA (On-Site) Role Type: - 12+ Months (Contract) Job Description: Defining and implementing test plans, developing System Verilog /UVM based unit level test benches, including stimulus, checkers, monitors and assertions, analyzing and debugging regression fails, and developing and analyzing functional coverage on North Bridge / Data Fabric Design. Key skills are software (System Verilog, C/C++, object-oriented programming, scripting (e.g. Perl), x86 a
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