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Senior Verification Engineer - Contract W2 position

Remote • Posted 4 hours ago • Updated 4 hours ago

Contract W2

6 Months

Remote

$60 - $65/hr

Fitment

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Job Details

Skills

Verification Engineer
UVM
IEEE 1149.1
IEEE 1500
IEEE 1687

Summary

Job Title: Senior Verification Engineer

Location: Remote

Duration: 6 Month s Contract

Job Description: Responsibilities:
8-15 years of experience in ASIC/SoC verification.

Proven experience in at least one or more of:

UVM-based verification environment development.

IJTAG/DFT infrastructure verification.

TAP Controller and JTAG verification.

ICL/PDL development and validation.

Verification of IEEE 1149.1, IEEE 1500, and IEEE 1687 compliant designs.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 90798281
Position Id: 9119534
Posted 4 hours ago

Contact the job poster

Saurabh Bhatt

Recruiter @ SunRay Enterprise Inc

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Remote

•

11d ago

Tittle : Sr. ASIC/SoC Design verification Engineer Work Location:Fully remote Duration:8 months Terms:W2 Contract Authorized US Worker- s Key Skills: Application-Specific Integrated Circuit (ASIC), System-on-Chip (SoC), SystemVerilog and UVM (Universal Verification Methodology) Position Summary: As aSenior Verification Engineeron the ASIC & Networking team, you support clients first in-house silicon program, which comprises a high-throughput modem and a DSP-intensive digital beamformer with fir

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7d ago

Job Description: Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-la

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Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

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7d ago

Position : ASIC Verification Engineer (UVM & GLS Focus) Location : Remote is fine Number of Positions : 7 Must-Have Skills Strong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock

Easy Apply

Contract

Depends on Experience

ASIC Verification Engineer (UVM & GLS Focus)

Remote

•

Today

Must-Have SkillsStrong end-to-end UVM expertise with hands-on experience building verification environments from scratch, including testbench architecture, agents, sequences, monitors, scoreboards, checkers, assertions, coverage models, and regression automation.Extensive Gate-Level Simulation (GLS) experience including SDF annotation, timing validation, X-propagation analysis, reset/clock synchronization issues, power-up sequence validation, and debug of post-synthesis/post-layout simulation fa

Easy Apply

Contract

65 - 70

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Senior Verification Engineer - Contract W2 position

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Job Details

Skills

Summary

Saurabh Bhatt

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