Formal Verification Engineer

San Jose, CA, US • Posted 2 days ago • Updated 1 day ago
Full Time
No Travel Required
On-site
160000 - 170000/yr
Fitment

Dice Job Match Score™

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Job Details

Skills

  • SystemVerilog
  • Jasper
  • Formal Verification

Summary

We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools.

Key Responsibilities:

  • Develop formal verification strategies and methodologies
  • Write SystemVerilog Assertions (SVA)
  • Perform property checking, equivalence checking, and CDC/RDC analysis
  • Identify corner cases missed in simulation
  • Collaborate with RTL teams for design improvements

 

Required Skills:

  • Strong knowledge of formal verification tools (Jasper, VC Formal, etc.)
  • Expertise in SVA and property specification
  • Solid understanding of digital design and logic reasoning

 

Good to Have:

  • Experience in low-power/CDC verification
  • Exposure to security verification
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10217521
  • Position Id: 9012840
  • Posted 2 days ago
Contact the job poster
LK

Lokesh Kotturu

Recruiter @ Ztek Consulting
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