San Jose, California
•
2d ago
Job Title: Formal Verification Engineer Location: San Jose, CA Full Time Job Description: We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools. Key Responsibilities: Develop formal verification strategies and methodologies Write System Verilog Assertions (SVA) Perform property checking, equivalence checking, and CDC/RDC analysis Identify corner cases missed in simulation Collaborate with RTL teams for
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