Senior Design Verification Engineer – SystemVerilog / UVM / AXI – San Diego

San Diego, CA, US • Posted 20 hours ago • Updated 20 hours ago
Contract Independent
Contract W2
Contract Corp To Corp
No Travel Required
Able to Sponsor
On-site
Depends on Experience
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Design Verification
  • SystemVerilog
  • UVM
  • Verilog
  • ASIC Verification
  • RTL Verification
  • Testbench Development
  • Functional Coverage
  • Code Coverage
  • Assertions (SVA)
  • AXI
  • AHB
  • VCS
  • Scoreboards
  • Checkers
  • Coverage Closure
  • Digital Design Verification
  • SoC Verification

Summary

Job Title: Senior Design Verification Engineer (SystemVerilog / UVM)

Location: San Diego, CA
Experience Required: 8+ Years
Employment Type: Full-Time / Contract

Job Description:
We are seeking an experienced Design Verification Engineer with strong expertise in SystemVerilog and UVM methodology. The candidate will be responsible for verifying complex ASIC/RTL designs and developing robust verification environments across the full verification lifecycle.

Key Responsibilities:
• Perform digital design verification for ASIC and RTL designs across the full verification lifecycle
• Develop functional and code coverage plans to ensure thorough design verification
• Plan, develop, and debug verification tests
• Develop test cases, checkers, and scoreboards for verification environments
• Build complete testbenches using SystemVerilog and UVM methodology
• Work with simulators to run and debug test scenarios
• Implement assertions and coverage metrics to achieve coverage closure
• Verify complex digital designs including modem processors and high-speed interfaces
• Perform verification for on-chip protocols such as AHB and AXI
• Collaborate with design and architecture teams to debug and resolve design issues

Required Skills:
• 8+ years of experience in Design Verification
• Strong expertise in Verilog and SystemVerilog
• Hands-on experience with UVM methodology
• Experience in ASIC and RTL verification
• Experience in developing verification environments, testbenches, and coverage models
• Strong debugging and problem-solving skills

Protocols:
• AHB
• AXI

Tools & Technologies:
• UVM Methodology
• Verilog
• SystemVerilog
• Simulation tools such as VCS

Preferred Skills:
• Experience verifying modem processors or complex SoC designs
• Strong understanding of coverage-driven verification
• Experience with assertions and functional coverage

Soft Skills:
• Strong communication and collaboration skills
• Ability to work in a fast-paced development environment

Application Process:
Interested candidates can apply directly through Dice or share their updated resume for immediate consideration.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91153480
  • Position Id: 2026-5
  • Posted 20 hours ago
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