Design Verification Engineer

Data Fabric verification engineer: 5 to 20 years of experience PREFERRED EXPERIENCE: Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes. Exposure to RTL design, software development, formal verification, or other related domains. Good understanding of computer organization/architecture. Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics KEY RESPONSIB

Please look for design engineers with power analysis experience Verification engineers with power aware verification or low power design verification experience. ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling and automation. The ideal candidate will play a crucial role in the analysis of power consumption, identifying hardware events that correlate

.Validate ML-Coprocessor, display SOC, Mixed Signal SOC, and IP. Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW. Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies .Execute bring-up/debug, workload enablement, and ML accelerator SW stack validation Perform performance and power characterization under real ML workload

Job Overview: We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power op