ASIC Engineer

Summary

The ASIC Engineer is responsible for designing ASIC and FPGA used in our products. Be a team player and works with other engineering teams (software, hardware and system) on architecture and system validation. Responsible for supporting our ASIC/FPGA development effort including FPGA synthesis, Timing constraints, ASIC backend support, FPGA low level tests on prototyping platform.

Essential Duties & Responsibilities

Will be using the tools below:

• System Verilog
• Perl, awk or sed scripting
• GIT version control system
• Cadence simulator, linter and code coverage
• Intel FPGA tools (Quartus)
• Experience with Quartus Platform Designer and DDR memory interface.
• Oscilloscope
• ASIC timing analysis tool (Prime Time or other)

Skills and Abilities

• Basic knowledge of C language, for the purpose of writing test code for ASIC and FPGA validation
• Good scripting capability with Perl, Awk, sed etc....
• In depth experience with ASIC timing constraints (sdc)
• In depth experience with ASIC timing analysis
• Experience with ASIC simulation, Cadence XCELIUM preferably
• Time management and capability to ensure that business goals are timely met
• Must be proactive, taking initiative and working in a collaborative team environment
• Must demonstrate excellent problem-solving and decision-making skills.
• Ability to work in a fast-paced environment
• Excellent verbal and written communication skills
• Foster a professional attitude and demonstrate integrity and flexibility
• Entrepreneurial, rapid learner, inquisitive, and persistent
• Excellent organizational skills and attention to detail
• Ability to efficiently use video conferencing tools to manage interactive meetings and webinars as needed

Work Experience

• Minimum of 10 to 15 years of ASIC & FPGA design.
• Proven successful experience completing multiple ASIC tape-out, preferably as a technical chip leader.
• Proven successful experience completing multiple FPGA designs for ASIC prototyping and products.
• Experience working with other teams (software, hardware, and system).
• Nice to have High speed transceivers interfaces such as CPRI or JESD204B
• Nice to have DDR4/DDR5 experience
• Arria 10 FPGA experience preferable