Analog Simulation/Env Automation CAD Engineer

Interested in how Apple designs the world's most advanced silicon? Want to write software that helps create the next generation of processors and enables the next astonishing Apple innovation? There's no telling what you could accomplish at Apple! We're looking for an engineer who will bring passion for hardware and strong programming skills to our team of CAD engineers. \\n\\nIn this role, you will have the opportunity to directly influence the circuit design on various technology nodes and develop CAD flows for analog circuit SPICE simulation, netlist, design environment, and analyze waveforms, results data processing. Your contributions will be instrumental in the analog, mixed-signal, and RF circuit design teams. You will assist in developing and validating custom SPICE simulation flows, enhancing the custom design environment, and conducting results analysis.

In this highly visible role, your primary responsibilities will include:\n\nSolving issues related to transistor level simulations on Analog, RF and Microwave applications with Spice simulators on command-line and Virtuoso environment.\n\nAssist designers in solving tool issues related to Analog Design Environment (ADE/XL, Maestro, OCEAN etc.) and develop automation flows.\n\nContribute to methodology on SPICE simulation and modeling techniques related to circuits, thereby influencing the advancement of a variety of technology nodes.\n\nDevelop next generation in-house EDA CAD flow solutions related to Analog and Mixed-signal simulations.

Exposure to SPICE simulation and design environment to handle flow/tool issues in Analog/RF circuit domain.\n\nRelevant internship or research experience.\n\nProgramming/scripting skills in Python or Shell. \n\nGood written and verbal communication skills, and the ability to collaborate well with cross-functional teams.\n\nMinimum requirement of BS degree.

Knowledge of circuit simulations with Analog/RFIC design and/or related CAD/automation support areas involving various technology nodes and tape out. \n\nExposure to Cadence ADE environment including knowledge of Virtuoso Schematic Editor, PDK, Virtuoso Analog Design Environment (ADE-L/XL/GXL/Maestro), SPICE simulators.\n\nKnowledge of device level SOA checks, PVT, Reliability/aging analysis, ERC asserts.\n\nUnderstand custom IC designs, and knowledge of Pre/Post-layout simulations, basic understanding of PDK, Spice models.