Senior ASIC Verification Engineer (SystemVerilog/UVM)

We are hiring for a well-funded, late-stage semiconductor innovator developing high-performance programmable DSP solutions powering next-generation AI data center and cloud infrastructure.

This is a senior-level opportunity to work on advanced ASIC/SoC development in a high-growth, engineering-driven environment. The ideal candidate will have deep hands-on experience in block and system-level verification using modern methodologies.

Mandatory Requirements (Strictly Enforced)

• Must have current and recent experience as a Verification Engineer

• Minimum 10+ years total experience

• At least 7+ years of hands-on verification experience

• Must have completed 2 or more full block/system-level verification cycles

• Strong, in-depth knowledge of VLSI verification flows, languages, and concepts

• Proven experience in functional block/cluster-level testing

• Deep expertise in SystemVerilog and UVM

• Stable employment history required (no frequent job changes)

• No employment gaps

Candidates who do not meet these criteria will not be considered.

Technical Responsibilities

• Plan and execute verification of complex digital design blocks

• Develop and maintain UVM/SystemVerilog-based verification environments

• Implement constrained random and coverage-driven verification strategies

• Define and track functional, code, and corner-case coverage metrics

• Debug RTL functionality in collaboration with design engineers

• Drive coverage closure and participate in full verification cycles through sign-off

Required Technical Skills

• SystemVerilog (advanced proficiency)

• UVM (preferred) or OVM/eRM

• ASIC or SoC verification

• Coverage-driven verification (CDV)

• Constrained Random Verification (CRV)

• Assertion-Based Verification (SVA preferred)

• Experience with tools such as VCS, QuestaSim, or equivalent

Preferred Qualifications

• Experience verifying high-speed data path designs

• Ethernet protocol verification experience

• DSP or networking silicon exposure

• Experience in analog/mixed-signal collaborative environments

• Strong documentation and communication skills (test plans, coverage reports)

Additional Information

• Onsite in Austin, TX – 5 days per week (non-negotiable)

• Competitive compensation + meaningful equity participation

• Full benefits package

• H1B sponsorship available

Ideal Candidate Profile

This role is ideal for a Senior or Staff-level ASIC/SoC Verification Engineer who has independently built UVM-based verification environments, driven coverage closure, and completed multiple full verification cycles in complex semiconductor programs.

If you would like to be considered, please submit your resume detailing verification environments built, verification cycles completed, and specific protocol experience.