Senior Validation Engineering Manager

Senior Validation Engineering Manager

A leading chip and silicon IP provider is looking to hire a Validation Manager to join its Memory Interface Chip business unit. In this full-time role, you’ll collaborate with some of the industry’s top engineers and innovators to develop products that make data faster and more secure.

As the Validation Manager, you will lead and work closely with your team to validate and characterize high-performance buffer chip products. The ideal candidate will have a strong background in processor-to-memory interfaces, including DDR topologies and protocols, as well as expertise in high-speed signaling, signal integrity, and power integrity concepts.

Responsibilities:

• Partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, and procurement experts
• Own, develop and continuously adapt and improve validation methodologies and technologies to continuously improve design validation coverage and time-to-market
• Partner with Design, Architecture, Verification, and Operation teams to deliver high-quality buffer chip products
• Work with external partners in sourcing test equipment, PCB manufacturing and assembly.
• Lead and manage the bench validation team to execute hands-on validation and characterization of memory buffer chips
• Perform hands-on bench validation and lab automation software development
• Develop test methodologies to validate silicon designs against specifications

Qualifications:

• Track record of growing organizations with focus on organization and validation methodology development
• Demonstrated ability with project planning, resource allocation, capital and operational budgeting and Develop test methodologies for validating silicon designs against specifications.
• Knowledge of processor / memory device architecture and specifications.
• Expert on Python programming, focused on validation characterization automation, and data analysis.
• Experience in Bench testing, with knowledge and experience on ATE or/and System Testing is a plus
• Minimum 5+ years of hands-on bench validation experience is required
• Proven experience with DDR4/DDR5 and processor/memory system architecture
• Demonstrated leadership experience, either as a manager (2–5 direct reports) or as an IC with team leadership responsibilities

Education: B.S. or M.S. in Electrical Engineering

Location: Atlanta, GA; San Jose, CA; United States

Duration: Fulltime

Salary Range: $170-$210K (DOE)

No 3rd party agencies or C2C

Abel Lara | OSIJOBS