Hi , This role is a Full Time / Permanent . Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer Location : Mountain View CA Qualifications 8+ years delivering ASIC/SoC IP designs. 6+ years of hands-on digital design, RTL, and microarchitecture experience. Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade-offs. Experience with NoC/interconnect and high-throughput/low-latency designs. Experience with SoC

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are building the next generation of solid-state drive controllers at Micron, where cutting-edge ASIC design meets high-performance storage innovation. Our team works across the full silicon life

Principal ASIC Design Engineer RTL / Microarchitecture / High-Performance Networking Overview Seeking a Principal ASIC Design Engineer to own front-end design for complex, high-performance silicon used in advanced networking and AI infrastructure. This role will work closely with architecture, verification, emulation, DFT, and physical design teams to translate product requirements into robust microarchitecture and production-ready RTL. The ideal candidate is a hands-on technical leader with dee

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged o