ASIC DFT (Design for Test) Lead

Role:            ASIC DFT (Design for Test) Lead

Location:     Remote

Duration:    12+ months (possibly extending longer based on project timelines)

Candidate Responsibilities:

·       Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug

·       Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.

·       Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

·       The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Minimum Requirements: (“Must have” Qualifications)

·       You will be part of the Silicon One optics development organization as a DFT Technical Lead in Carlsbad, CA with a primary focus on Design-for-Test.

·       You will develop and implement DFT features - ATPG, scan compression, memory BIST, memory repair to ensure high quality testable and manufactural designs.

·       You will contribute to the full product cycle from pre-silicon design to post-silicon debt and production qualification. You will collaborate across multiple teams throughout the silicon life cycle. Starting from implementing DFT features to lead debugging and root cause analysis of silicon failures to improve yield and reliability.

·       Bachelor''s or a Master''s Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.

·       Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high-speed digital/analog macros

·       Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, TempPrimetime

·       At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production

·       Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production

·       Ability to quickly learn new concepts and adapt to evolving technologies

·       Excellent communication and presentation skills

·       Strong attention to detail and system level understanding of networking and photonic solutions

·       Our chips are strategically placed in Silicon one AI infrastructure, powering next generation network devices to support advanced AI workloads.