Static Timing Analysis Engineer

San Jose, CA, US • Posted 2 days ago • Updated 2 days ago
Full Time
No Travel Required
On-site
150,000+
Fitment

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Job Details

Skills

  • ASIC
  • RTL
  • Static Timing Analysis
  • Synopsys
  • Debugging
  • Energy
  • FC
  • Problem Solving
  • Integrated Circuit
  • Perl
  • Regulatory Compliance
  • TCM
  • Teamwork
  • Optimization
  • Collaboration
  • Effective Communication
  • Place And Route
  • Conflict Resolution
  • Attention To Detail
  • Scripting
  • Tcl
  • System On A Chip
  • Timing Closure

Summary

Position: Static Timing Analysis Engineer

Location - San Jose, CA, USA

What You will Do:

Develop and validate timing constraints for intricate SoC designs.

Expertise in Synthesis, Equivalency Checking and STA

Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.

Experience with Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA

Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.

Conduct pre-route timing checks and quality of results (QoR) analysis.

Automate timing analysis processes using scripting languages such as Tcl or Perl.

Provide guidance on clock tree synthesis and optimization for energy-efficient designs
Ensure compliance with timing signoff checklists and criteria.

 

What You Will Bring:

Experience with high-complexity silicon in advanced technology nodes.

Familiarity with timing constraint development for hierarchical designs.

Knowledge of clock tree planning and implementation for SoCs.

Experience with timing ECO creation and final timing signoff.

Proficiency in using STA tools (e.g., PrimeTime, TCM, Tempus) and scripting languages (e.g., Tcl, Perl).

Proficiency in using synthesis tools (Genus)

Must have Full Chip (Top Level) and Block Level and Multi-voltage Timing Closure experience.

Debug and Fix Timing Issues
This STA engineer needs to do Synthesis, Equivalency Checking and STA

Good understanding of Timing Constraints, Exceptions, CTS and clock constraints, Multi-Mode Multi-Corner timing closure expertise.

Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA

Strong understanding of ASIC design flows, including RTL and place-and-route.

Excellent problem-solving skills and attention to detail.

Effective communication and teamwork abilities.

Bachelors and 8+ years of related experience; at this level post-graduate coursework may be desirable or Master’s degree and 6+ years of related experience or PhD and 3+ years of related experience.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90884546
  • Position Id: 9020018
  • Posted 2 days ago
Contact the job poster
SS

Shaik Shariff

Director of Recruitment @ iTechStack
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