Lead Software Engineer

San Jose, CA, US • Posted 7 days ago • Updated 2 hours ago
Full Time
On-site
USD $114,800.00 - 213,200.00 per year
Fitment

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Job Details

Skills

  • DSG
  • Semiconductors
  • System On A Chip
  • Cadence
  • Debugging
  • Place And Route
  • Code Optimization
  • Strategy Development
  • Data Modeling
  • API
  • Problem Solving
  • Conflict Resolution
  • C
  • C++
  • Software Development
  • Linux
  • Data Structure
  • Communication
  • Electrical Engineering
  • Computer Science
  • Routing
  • Algorithms
  • 3D Computer Graphics
  • Multithreading
  • Research and Development
  • Integrated Circuit
  • Internal Communications
  • IC
  • Physical Data Model
  • Tcl
  • Scripting
  • Sales

Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This Position is in our Digital & Signoff Group (DSG)

DSG addresses one of the biggest and most competitive market segments in the semiconductor industry: digital system on chip (SoC) implementation and signoff. Join some of the brightest minds in this area to drive advancements in technologies including digital front-end design, IC digital implementation, and silicon signoff and verification.

Position Description

Cadence Design Systems is looking for a highly motivated Software Engineer to work with the Innovus Research and Development engineering team in the IC Digital business unit. You will be part of a team responsible for designing, developing, troubleshooting, debugging and supporting Place and Route Software.

Development responsibilities will include: logic gate placements, interconnect routing engine development, code optimization & strategy development, data-model enhancements, text file parser development & enhancement, and API/Class definition & enhancement.

Minimum Qualifications:
Highly technical engineer with excellent problem solving skills
C/C++ software development experience in Linux environment
Strong understanding and extensive usage of data structures and algorithms
Great communication skills and a strong desire for working with customers
MS (Ph.D. track a plus) in Electrical Engineering, Computer Science.

Preferred:
Knowledge of interconnect routing algorithms, 3D-IC integration, timing analysis and multithreading is a strong plus.
Prior R&D experience working on IC physical designs tools
Hands on experience using the above physical design tools for design closure and knowledge of physical design flows a plus.
Experience with Tcl and other scripting languages

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: CADENCE
  • Position Id: 7460a1533f2e797c4d9af6db59e52556
  • Posted 7 days ago
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