Senior Design Verification Engineer

Design Verification (DV) Engineer
Key Responsibilities

• Develop and maintain UVM-based SystemVerilog testbenches
• Create reusable verification components and environments
• Develop and execute verification plans for subsystem and block level
• Debug RTL issues and collaborate closely with design
• Contribute to end-to-end validation flows
• Drive coverage closure

Required Qualifications

• Strong hands-on expertise in UVM and SystemVerilog
• Experience with ARM-based protocols including:
• APB
• AXI (no CHI/coherency required)
• Strong debugging and testbench architecture skills
• Experience writing assertions and functional coverage

Highly Preferred

• Formal verification expertise
• Experience in subsystem-level DV

Ability to independently own benches