Company:Qualcomm Technologies, Inc.
Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:We are seeking a highly skilled Senior Device Engineer with deep expertise in low-power interconnects and SiPh/optical interfaces. This role requires close collaboration with internal design, CAD, yield, and test teams, as well as external foundries and test partners. You will develop and implement low-power, high-density interconnect technologies-electrical and optical-to support advanced memory ICs and chiplets for the AI era (training and inference). The ideal candidate has strong expertise in CMOS/photonic interconnect technologies, circuit design, and simulation, PIC simulation and optimization, PDK development, and tape-out flows.
ResponsibilitiesLow-Power Interconnect Design- Design and optimize low-power chiplet-to-chiplet interconnects using copper (TSVs, micro-bumps) and optical waveguides.
- Develop and simulate PIC components, including modulators, photodetectors, multiplexers, fiber-to-chip couplers, and lasers/uLED.
- Construct and validate optical link budgets, ensuring robust Tx/Rx signal integrity (IMDD/Coherent).
FEM Simulation & AI-Driven Optimization- Perform optical/RF simulations using Ansys Lumerical (FDTD, MODE, INTERCONNECT), COMSOL, or similar tools.
- Build and apply AI-based inverse design workflows to discover novel, high-performance photonic or RF structures.
- Model and mitigate manufacturing-induced variations and assess their impact on interconnect device performance for fab tape-outs.
Process, PDK, and Characterization- Partner with test, yield, and design teams to address fab-related issues for new optical/SiPh processes and products.
- Support technology benchmarking and model validation using test IP cores for PIC structures and interconnect Rx/Tx building blocks.
- Support end-to-end tape-out activities including mask reviews, database preparation, and validation.
- Lead wafer- and die-level optical characterization including automated probe station measurements of bandwidth, insertion loss, and thermal behavior.
Cross-Functional Collaboration- Interface with global CAD, design, SQE, YMT, package, and reliability teams to resolve issues effectively.
- Collaborate with external IP vendors, fabs, OSATs, and silicon/III-V service partners to ensure timely execution.
Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Preferred Qualifications:- Minimum 2 years of experience in silicon photonics, optics, high-speed interconnects, or PIC design.
- Hands-on experience with interconnect circuit design, PIC design/simulation, and PEX/EM tools (Cadence, ADS, Lumerical, COMSOL).
- Knowledge of digital/RF/MSA CMOS design flows is a plus.
- Experience with technology development, benchmarking, and model validation using test IP for RF/PIC/analog applications.
- Strong understanding of interconnect link-budget calculations, optical communications, and AI-driven simulation workflows.
- Excellent communication skills with demonstrated ability to meet deadlines and solve problems efficiently.
- Experience with hardware description languages such as Verilog or VHDL.
- Experience using statistical tools and scripting languages (Python, Tcl, JMP).
- Understanding of CMOS/SiPh process flows, including lithography, etch, and deposition.
- Knowledge of optical/SiPh process modules is a strong plus.
Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).
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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
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