VLSI CAD Engineer

Cupertino, CA, US • Posted 15 hours ago • Updated 3 hours ago
Full Time
On-site
USD $154,271.00 - 225,300.00 per year
Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Job Details

Skills

  • VLSI
  • Innovation
  • Collaboration
  • DV
  • Regression Testing
  • Payments
  • Electrical Engineering
  • Verilog
  • SystemVerilog
  • UVM
  • Automated Testing
  • Continuous Monitoring
  • Data Quality
  • HDL
  • ROOT
  • Scripting
  • Resource Allocation
  • Workflow
  • Cloud Computing
  • Machine Learning (ML)
  • Scheduling
  • RTL
  • Regression Analysis

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Execute RTL regression tests using industry-standard verification tools like Verilog/System Verilog HDL simulators and system verification languages (e.g., UVM). Monitor regression results, analyze coverage data, and identify failed tests. Use coverage tools to measure and enhance functional coverage. Collaborate with the DV team to understand the root causes of regression failures. Utilize debuggers to step through RTL code and identify issues. Develop and implement new solutions to address regression issues, enhance verification efficiency, or optimize computer usage using ML-based techniques. Build ML models that predict test failures or optimize resource allocation. Implement performance optimizations in regression runs using tools like task parallelism libraries or cloud-based verification platforms. Maintain and enhance the existing RTL regression system to ensure its reliability and efficiency. Implement automation scripts to streamline regression setup, execution, and result analysis. Propose innovative solutions and collaborate with the DV team to implement them effectively. Explore and apply ML-based techniques to optimize computer usage in regression testing. Predict test failure rates which involve building models, optimizing test scheduling, or identifying critical code paths for focused verification. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $154,271 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: ;br>
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master's degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.

Experience and/or education must include:

Executing RTL regression tests using Verilog/SystemVerilog HDL simulators and UVM-based verification environments

Built and maintained self-retraining ML pipelines for automated test case generation, with scheduled daily triggers and continuous monitoring of data quality metrics and runtime performance fluctuations.

Utilizing RTL debuggers to step through HDL code and identify root causes of regression failures

Developing automation scripts to streamline regression setup, execution, and result analysis

Building machine learning models to predict test failures and optimize resource allocation in verification workflows

Implementing performance optimizations using task parallelism libraries or cloud-based verification platforms

Applying ML-based techniques to optimize test scheduling and identify critical code paths for focused verification

Maintaining and enhancing RTL regression infrastructure to ensure reliability and efficiency of verification systems

Preferred Qualifications

N/A
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90733111
  • Position Id: fc898f545407a4c42a00b35a98e9e99e
  • Posted 15 hours ago
Create job alert
Never miss an opportunity! Create an alert based on the job you applied for.