DFT Lead

DFT Lead

Location : San Jose ,CA or Chandler, Arizona ( Hybrid Work)

Long Term

Responsibilities

Manage DFT requirements across architecture, design, and product teams to ensure coverage, die cost, test cost and DFT integration requirements are met at the block and full chip level. Define, implement and validate DFT features at the FPGA full chip and sub-systems level.
Collaborate closely with cross functional teams to support DFT insertion, synthesis, scan insertion, place-and-route, static timing analysis, timing closure, power analysis during test and quantifying full chip test coverage.
Establish and maintain DFT design and insertion guidelines and documents best practices for all development teams to follow.
Be current with emerging technologies and methodologies in DFT and incorporate them into the FPGA to continuously improve test cost and quality.
Work with Test and Product engineers to support development of firmware targeted test patterns, ATPG and mBIST test feature validation processes, and silicon debug activities.
Communicate project status and progress to chip lead and engineering management

Requirements/Qualifications

Bachelors or Masters in engineering field
15+ years of DFT engineering experience through DFT pre and post silicon cycles
Experience in creating and implementing complex FPGA/SoC DFT architecture in advanced technology nodes
Expert level knowledge about IJTAG and JTAG test access, Streaming Scan Network (SSN), scan compression and insertion, SAF/TDF/PDF ATPG, memory BIST and repair, logic BIST, MISRs, at-speed testing of SoC/FPGA, fault simulation, quantifying full chip test coverage, DFT mode timing constraints and power control during test.
Familiar with DFT verification, silicon debug, memory and scan diagnostics.
Experience in PHY, high-speed IO, digital communication and functional test development
Good understanding of Verilog, synthesis, physical implementation and STA
Good understanding of verification methodology