Power Engineer (RTL Design)

Job Overview: We are looking for a highly skilled Physical Design Engineer to work at block level and/or top level for high-performance ASICs, SoCs, and custom silicon chips with strong scripting skills. The ideal candidate will be responsible for various aspects of the backend VLSI design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. The role requires expertise in EDA tools, physical verification methodologies, power op

.Validate ML-Coprocessor, display SOC, Mixed Signal SOC, and IP. Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW. Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies .Execute bring-up/debug, workload enablement, and ML accelerator SW stack validation Perform performance and power characterization under real ML workload

Data Fabric verification engineer: 5 to 20 years of experience PREFERRED EXPERIENCE: Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes. Exposure to RTL design, software development, formal verification, or other related domains. Good understanding of computer organization/architecture. Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics KEY RESPONSIB

Test Program Ownership: Experience testing complex PCB assemblies (system level or high density boards). Proven ability to troubleshoot issues across hardware, fixtures, and test software domains. Act as the single point of accountability (Captain) for test execution, stability, and performance. Own and manage the end to end manufacturing test program for complex PCB assemblies Background in RF measurements and signal integrity and Electrical and digital circuit behavior Test Systems & Tools