seeking a highly experienced Senior Staff CAD Engineer to lead and advance EDA design flows, CAD infrastructure, and signoff methodologies for next-generation semiconductor products. This individual will serve as the technical authority for advanced-node IC design environments, enabling successful development and tapeout of RF, Analog, High-Speed IO, and Digital SoC designs on cutting-edge FinFET technologies.
The ideal candidate will have deep expertise in advanced-node PDK management, Cadence design environments, physical verification, signoff automation, and EDA infrastructure management.
Key ResponsibilitiesPDK & Infrastructure Management
- Install, qualify, and maintain advanced foundry PDKs for FinFET technologies (5nm, 3nm, and 2nm).
- Manage EDA infrastructure, compute clusters, license servers, and grid utilization.
- Optimize tool performance, resource allocation, and design environment reliability.
Design Flow Development
- Develop, deploy, and support Cadence Virtuoso and Innovus environments.
- Build scalable analog, mixed-signal, RF, and high-speed IO design flows.
- Collaborate closely with design teams to improve productivity and design quality.
Physical Verification & Signoff
- Develop and maintain automated signoff methodologies using:
- Siemens Calibre (DRC, LVS, PERC)
- Synopsys StarRC
- Ensure first-pass silicon success through robust verification processes.
Reliability Verification
- Deploy and support:
- EMIR (Electromigration & IR-Drop) analysis
- PERC flows
- Advanced reliability verification methodologies
- Support advanced-node design signoff and validation.
Automation & Tool Development
- Create automation frameworks and utilities using:
- SKILL
- Perl
- Python
- Tcl
- Bash/Shell
- Improve engineering productivity by reducing manual effort and streamlining workflows.
- Serve as the primary escalation point with EDA vendors and foundries.
Required Qualifications
- Bachelor''s or Master''s degree in:
- Electrical Engineering
- Computer Engineering
- Computer Science
- Related Engineering Discipline
- 5+ years of hands-on IC CAD / EDA experience.
Advanced Node Experience
- Direct experience supporting:
- 5nm
- 3nm
- 2nm FinFET technologies
- Strong knowledge of advanced-node signoff methodologies.
EDA Tools Expertise
- Siemens Calibre
- DRC
- LVS
- PERC
- Synopsys StarRC
- Cadence Virtuoso
- Cadence Innovus
Automation Skills
- Strong expertise with:
- SKILL
- Perl
- Working knowledge of:
- Python
- Tcl
- Bash/Shell
Infrastructure Experience
- Linux administration
- Compute grid environments
- LSF
- SGE
- Version control systems
- Perforce
- ICManage
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