Network Cluster Architect - Data center Infrastructure

The Data Center Hardware Engineering team is responsible for designing and deploying Apple's next-generation compute infrastructure at scale. Our team works on projects from early design conception through mass production, focusing on cluster-level network architecture, data hall power distribution, rack-level electrical systems, and server hardware design. This is a highly cross-functional organization that collaborates closely with mechanical engineering, power systems, software and firmware teams, silicon design, hardware validation, and reliability engineering to deliver high-performance, energy-efficient compute solutions that power Apple's services and AI/ML workloads. \\n\\nWe are seeking experienced Systems Architects who can think holistically about infrastructure challenges-from the data center level down to individual components-and drive technical innovation through data-driven analysis and executive-level communication.\\n\\nCome join us!

The Network Cluster Architect will be responsible for owning and advancing critical investigations spanning cluster-level network topology, hall-level power distribution, rack-level electrical systems, and server hardware electronics design. This role involves coordinating with cross-functional teams including electrical validation, software engineering, and hardware test teams to aggregate validation results and verifying design assumptions.

Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field\n\n8+ years of relevant industry experience in hardware architecture, electrical engineering, network architecture, or data center infrastructure design\n\nStrong EE fundamentals, grounded in a solid understanding of electromagnetics and first principles\n\nDeep understanding of cluster and data hall level infrastructure, including network topology, power distribution systems, PDUs, busways, and electrical safety standards\n\nWorking knowledge of design and validation requirements for common digital interfaces: I2C/SMBus, SPI, JTAG, USB, PCIe, Ethernet (QSFP, OSFP), DDR Memory, storage interfaces\nExperience with high-speed board design and can guide SI/PI simulations

Master's degree or Ph.D. in Electrical Engineering, Computer Engineering, or related field with 10+ years of relevant industry experience\n\nFunctional experience defining and deploying datacenter cluster networking architectures over highly dense mesh networks and interconnected nodes for AI/ML workloads\n\nProven track record of deploying AI/ML experiences at scale in large-scale data centers with strong experience in modern ML architecture deployment\n\nStrong technical breadth across computer subsystem technologies: CPU, xPU, storage, memory, power delivery, high-speed networking, I/O, thermal management\n\nExposure to hyperscale data center environments and experience designing for high volume, high power, highly reliable and available systems\n\nFamiliarity with network cluster topologies for AI/ML workloads\n\nProven ability to coordinate with cross-functional teams to aggregate validation results and drive technical consensus\n\nStrong systems-level thinking with ability to understand dependencies across cluster, hall, rack, and server levels\n\nHigh-speed PCB design experience with 10+ layer boards, including material selection and SI/PI simulation tools\n\nUnderstanding of computer architecture and design tradeoffs, high-speed bus throughput and latency analysis, and interconnect fabric standards\n\nUnderstanding of power efficiency optimization at scale and sustainability initiatives\n\nPrior experience in mentoring engineers or leading technical teams in preferred\n\nSuperior written, verbal, and visual communication skills with demonstrated ability to present to executive leadership and influence strategic decisions\n\n\n\n\n