Design Verification Engineer

San Jose, CA, US • Posted 5 hours ago • Updated 5 hours ago
Contract W2
Contract Independent
1 Year
No Travel Required
Able to Sponsor
On-site
Depends on Experience
Fitment

Dice Job Match Score™

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Job Details

Skills

  • System Verilog
  • UVM

Summary

Momento USA is a global technology consulting, talent acquisition, and creative development firm that addresses clients' most pressing needs and challenges. We are currently looking for a Design Verification Engineer

 

Position: Design Verification Engineer

Duration: 12 months

Location: San Jose, CA - Onsite

 

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
  • Understand vendor IP configurations and handle handshake with internal IP team
  • Develop and maintain UVM/System Verilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
  • Drive coverage closure and sign-off by defining metrics, analysing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

  • 5+ years of design verification experience
  • You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
  • You have hands-on experience with industry-standard verification methodologies like System Verilog/UVM and understand how to build scalable, reusable testbenches.
  • You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
  • You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
  • You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong candidates may also have experience with

  • Experience handling vendors and integration of IP/VIP’s
  • UVM/System Verilog

 

 

 

Subia Khan

DESK: , EXT: 1032

w: e:

440 Benigno Blvd, Unit#A 2nd Floor. Bellmawr, NJ 08031

Interstate Business Park

Note: Momento USA is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10454196
  • Position Id: 9881-6220-1787760885
  • Posted 5 hours ago
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