FE Engineer

Austin, TX, US • Posted 6 hours ago • Updated 6 hours ago
Full Time
On-site
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Collaboration
  • Innovation
  • Intellectual Property
  • IP
  • System On A Chip
  • Macros
  • Timing Closure
  • Integrated Circuit
  • Physical Data Model
  • DFT
  • Electrical Engineering
  • Electronic Engineering
  • Computer Engineering
  • SystemVerilog
  • Verilog
  • Synopsys
  • Cadence
  • RTL

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Integrate Internal and external IP (Intellectual Property), designing system bus and control bus logic for connectivity of IP blocks to the main SOC infrastructure. Own the Integration Spec for the design project.

Integrate and optimize any memories and hard macros required for the block. Run synthesis, netlist generation, and timing closure for the block. Work closely with Chip Architecture, Design verification, Physical Design, DFT (Design for Test), and power teams to achieve first tape out success on designs. Develop and maintain methodology/flows/checks for owned designs. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.

40 hours/week.

Minimum Qualifications

Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.

Experience and/or education must include:

Using System Verilog or Verilog to write RTL for Integration components

Utilizing multiple clock domains, reset domains and applying techniques to fix the issues

Utilizing low power design concepts like clock gating, power gating and DVFS to meet low power design targets

Utilizing Synthesis tools from Synopsys or Cadence to use timing constraints to synthesize designs

Integrate RTL components into sub-systems interfacing with memories

Utilizing Design-for-test concepts to support scan insertion for overall testability

Utilizing CAD tools to ensure quality of design

Preferred Qualifications

N/A
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90733111
  • Position Id: cbc34575bdfea4075d026fdd3e7c515
  • Posted 6 hours ago
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